README revision 10152 
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9             A Tool to Model Caches/Memories
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11
12CACTI is an analytical tool that takes a set of cache/memory para-
13meters as input and calculates its access time, power, cycle 
14time, and area.
15CACTI was originally developed by Dr. Jouppi and Dr. Wilton
16in 1993 and since then it has undergone five major 
17revisions.
18
19List of features (version 1-6.5):
20===============================
21The following is the list of features supported by the tool. 
22
23* Power, delay, area, and cycle time model for 
24                  direct mapped caches
25                  set-associative caches
26                  fully associative caches
27                  Embedded DRAM memories
28                  Commodity DRAM memories
29                  
30* Support for modeling multi-ported uniform cache access (UCA)
31  and multi-banked, multi-ported non-uniform cache access (NUCA).
32
33* Leakage power calculation that also considers the operating
34  temperature of the cache.
35  
36* Router power model.
37
38* Interconnect model with different delay, power, and area 
39  properties including low-swing wire model.
40
41* An interface to perform trade-off analysis involving power, delay,
42  area, and bandwidth.
43
44* All process specific values used by the tool are obtained
45  from ITRS and currently, the tool supports 90nm, 65nm, 45nm, 
46  and 32nm technology nodes.
47
48Version 6.5 has a new c++ code base and includes numerous bug fixes.
49CACTI 5.3 and 6.0 activate an entire row of mats to read/write a single
50block of data. This technique improves reliability at the cost of  
51power. CACTI 6.5 activates minimum number of mats just enough to retrieve 
52a block to minimize power.
53
54How to use the tool?
55====================
56Prior versions of CACTI take input parameters such as cache
57size and technology node as a set of command line arguments. 
58To avoid a long list of command line arguments, 
59CACTI 6.5 lets users specify their cache model in a more 
60detailed manner by using a config file (cache.cfg).
61
62-> define the cache model using cache.cfg
63-> run the "cacti" binary <./cacti -infile cache.cfg>
64
65CACTI6.5 also provides a command line interface similar to earlier versions
66of CACTI. The command line interface can be used as
67
68./cacti  cache_size line_size associativity rw_ports excl_read_ports excl_write_ports 
69  single_ended_read_ports search_ports banks tech_node output_width specific_tag tag_width
70  access_mode cache main_mem obj_func_delay obj_func_dynamic_power obj_func_leakage_power
71  obj_func_cycle_time obj_func_area dev_func_delay dev_func_dynamic_power dev_func_leakage_power
72  dev_func_area dev_func_cycle_time ed_ed2_none temp wt data_arr_ram_cell_tech_flavor_in
73  data_arr_peri_global_tech_flavor_in tag_arr_ram_cell_tech_flavor_in tag_arr_peri_global_tech_flavor_in
74  interconnect_projection_type_in wire_inside_mat_type_in wire_outside_mat_type_in
75  REPEATERS_IN_HTREE_SEGMENTS_in VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in 
76  BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in PAGE_SIZE_BITS_in BURST_LENGTH_in
77  INTERNAL_PREFETCH_WIDTH_in force_wiretype wiretype force_config ndwl ndbl nspd ndcm 
78  ndsam1 ndsam2 ecc
79
80For complete documentation of the tool, please refer CACTI-5.3 and 6.0
81technical reports and the following paper,
82"Optimizing NUCA Organizations and Wiring Alternatives for 
83Large Caches With CACTI 6.0", that appears in MICRO 2007.
84
85We are still improving the tool and refining the code. If you
86have any comments, questions, or suggestions please write to
87us.
88
89Naveen Muralimanohar             Jung Ho Ahn        Sheng Li
90naveen.muralimanohar@hp.com      gajh@snu.ac.kr     sheng.li@hp.com
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