arch_const.h revision 10152:52c552138ba1
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31
32#ifndef ARCH_CONST_H_
33#define ARCH_CONST_H_
34
35typedef struct{
36        unsigned int capacity;
37        unsigned int assoc;//fully
38        unsigned int blocksize;
39} array_inputs;
40
41//Do Not change, unless you want to bypass the XML interface and do not care about the default values.
42//Global parameters
43const int  			number_of_cores =	8;
44const int  			number_of_L2s 	=	1;
45const int 			number_of_L3s	=	1;
46const int 			number_of_NoCs	=	1;
47
48const double 		archi_F_sz_nm	=	90.0;
49const unsigned int 	dev_type		=	0;
50const double 		CLOCKRATE 		= 	1.2*1e9;
51const double 		AF 				= 	0.5;
52//const bool 			inorder			=	true;
53const bool			embedded		=	false; //NEW
54
55const bool 			homogeneous_cores	= 	true;
56const bool 			temperature		=	360;
57const int			number_cache_levels	=	3;
58const int			L1_property		=	0; //private 0; coherent 1, shared 2.
59const int		 	L2_property		=	2;
60const bool	    	homogeneous_L2s	=	true;
61const bool		    L3_property		= 	2;
62const bool 			homogeneous_L3s	=	true;
63const double 		Max_area_deviation	=	50;
64const double	    Max_dynamic_deviation	=50; //New
65const int 			opt_dynamic_power	=	1;
66const int 			opt_lakage_power	=	0;
67const int		 	opt_area			=	0;
68const int			interconnect_projection_type	=	0;
69
70//******************************Core Parameters
71#if (inorder)
72const int opcode_length			= 	8;//Niagara
73const int reg_length			=	5;//Niagara
74const int instruction_length	=	32;//Niagara
75const int data_width			=	64;
76#else
77const int opcode_length			= 	8;//16;//Niagara
78const int reg_length			=	7;//Niagara
79const int instruction_length	=	32;//Niagara
80const int data_width			=	64;
81#endif
82
83
84//Caches
85//itlb
86const int itlbsize=512;
87const int itlbassoc=0;//fully
88const int itlbblocksize=8;
89//icache
90const int icachesize=32768;
91const int icacheassoc=4;
92const int icacheblocksize=32;
93//dtlb
94const int dtlbsize=512;
95const int dtlbassoc=0;//fully
96const int dtlbblocksize=8;
97//dcache
98const int dcachesize=32768;
99const int dcacheassoc=4;
100const int dcacheblocksize=32;
101const int dcache_write_buffers=8;
102
103//cache controllers
104//IB,
105const int numIBEntries			=	64;
106const int IBsize				=	64;//2*4*instruction_length/8*2;
107const int IBassoc				=	0;//In Niagara it is still fully associ
108const int IBblocksize			=	4;
109
110//IFB and MIL should have the same parameters CAM
111const int IFBsize=128;//
112const int IFBassoc=0;//In Niagara it is still fully associ
113const int IFBblocksize=4;
114
115
116
117
118const int icache_write_buffers=8;
119
120//register file RAM
121const int regfilesize=5760;
122const int regfileassoc=1;
123const int regfileblocksize=18;
124//regwin  RAM
125const int regwinsize=256;
126const int regwinassoc=1;
127const int regwinblocksize=8;
128
129
130
131//store buffer, lsq
132const int lsqsize=512;
133const int lsqassoc=0;
134const int lsqblocksize=8;
135
136//data fill queue RAM
137const int dfqsize=1024;
138const int dfqassoc=1;
139const int dfqblocksize=16;
140
141//outside the cores
142//L2 cache bank
143const int l2cachesize=262144;
144const int l2cacheassoc=16;
145const int l2cacheblocksize=64;
146
147//L2 directory
148const int l2dirsize=1024;
149const int l2dirassoc=0;
150const int l2dirblocksize=2;
151
152//crossbar
153//PCX
154const int PCX_NUMBER_INPUT_PORTS_CROSSBAR = 8;
155const int PCX_NUMBER_OUTPUT_PORTS_CROSSBAR = 9;
156const int PCX_NUMBER_SIGNALS_PER_PORT_CROSSBAR =144;
157//PCX buffer RAM
158const int pcx_buffersize=1024;
159const int pcx_bufferassoc=1;
160const int pcx_bufferblocksize=32;
161const int pcx_numbuffer=5;
162//pcx arbiter
163const int pcx_arbsize=128;
164const int pcx_arbassoc=1;
165const int pcx_arbblocksize=2;
166const int pcx_numarb=5;
167
168//CPX
169const int CPX_NUMBER_INPUT_PORTS_CROSSBAR = 5;
170const int CPX_NUMBER_OUTPUT_PORTS_CROSSBAR = 8;
171const int CPX_NUMBER_SIGNALS_PER_PORT_CROSSBAR =150;
172//CPX buffer RAM
173const int cpx_buffersize=1024;
174const int cpx_bufferassoc=1;
175const int cpx_bufferblocksize=32;
176const int cpx_numbuffer=8;
177//cpx arbiter
178const int cpx_arbsize=128;
179const int cpx_arbassoc=1;
180const int cpx_arbblocksize=2;
181const int cpx_numarb=8;
182
183
184
185
186
187const int numPhysFloatRegs=256;
188const int numPhysIntRegs=32;
189const int numROBEntries=192;
190const int umRobs=1;
191
192const int BTBEntries=4096;
193const int BTBTagSize=16;
194const int LFSTSize=1024;
195const int LQEntries=32;
196const int RASSize=16;
197const int SQEntries=32;
198const int SSITSize=1024;
199const int activity=0;
200const int backComSize=5;
201const int cachePorts=200;
202const int choiceCtrBits=2;
203const int choicePredictorSize=8192;
204
205
206const int commitWidth=8;
207const int decodeWidth=8;
208const int dispatchWidth=8;
209const int fetchWidth=8;
210const int issueWidth=1;
211const int renameWidth=8;
212//what is this forwardComSize=5??
213
214const int globalCtrBits=2;
215const int globalHistoryBits=13;
216const int globalPredictorSize=8192;
217
218
219
220const int localCtrBits=2;
221const int localHistoryBits=11;
222const int localHistoryTableSize=2048;
223const int localPredictorSize=2048;
224
225const double Woutdrvnandn	=30 *0.09;//(24.0 * LSCALE)
226const double Woutdrvnandp	=12.5 *0.09;//(10.0 * LSCALE)
227const double Woutdrvnorn	=7.5*0.09;//(6.0 * LSCALE)
228const double Woutdrvnorp  =50 * 0.09;//	(40.0 * LSCALE)
229const double Woutdrivern	=60*0.09;//(48.0 * LSCALE)
230const double Woutdriverp	=100 * 0.09;//(80.0 * LSCALE)
231
232/*
233smtCommitPolicy=RoundRobin
234smtFetchPolicy=SingleThread
235smtIQPolicy=Partitioned
236smtIQThreshold=100
237smtLSQPolicy=Partitioned
238smtLSQThreshold=100
239smtNumFetchingThreads=1
240smtROBPolicy=Partitioned
241smtROBThreshold=100
242squashWidth=8
243*/
244
245/*
246prefetch_access=false
247prefetch_cache_check_push=true
248prefetch_data_accesses_only=false
249prefetch_degree=1
250prefetch_latency=10000
251prefetch_miss=false
252prefetch_past_page=false
253prefetch_policy=none
254prefetch_serial_squash=false
255prefetch_use_cpu_id=true
256prefetcher_size=100
257prioritizeRequests=false
258repl=Null
259
260
261split=false
262split_size=0
263subblock_size=0
264tgts_per_mshr=20
265trace_addr=0
266two_queue=false
267
268cpu_side=system.cpu0.dcache_port
269mem_side=system.tol2bus.port[2]
270*/
271
272//[system.cpu0.dtb]
273//type=AlphaDT
274
275
276#endif /* ARCH_CONST_H_ */
277