110152Satgutier@umich.edu<?xml version="1.0" ?>
210152Satgutier@umich.edu<component id="root" name="root">
310152Satgutier@umich.edu	<component id="system" name="system">
410152Satgutier@umich.edu		<!--McPAT will skip the components if number is set to 0 -->
510152Satgutier@umich.edu		<param name="number_of_cores" value="2"/>
610152Satgutier@umich.edu		<param name="number_of_L1Directories" value="2"/>
710152Satgutier@umich.edu		<param name="number_of_L2Directories" value="0"/>
810152Satgutier@umich.edu		<param name="number_of_L2s" value="0"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
910152Satgutier@umich.edu		<param name="Private_L2" value="0"/><!--1 Private, 0 shared/coherent -->
1010152Satgutier@umich.edu		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
1110152Satgutier@umich.edu		<param name="number_of_NoCs" value="1"/>
1210152Satgutier@umich.edu		<param name="homogeneous_cores" value="1"/><!--1 means homo -->
1310152Satgutier@umich.edu		<param name="homogeneous_L2s" value="1"/>
1410152Satgutier@umich.edu		<param name="homogeneous_L1Directorys" value="1"/>
1510152Satgutier@umich.edu		<param name="homogeneous_L2Directorys" value="1"/>
1610152Satgutier@umich.edu		<param name="homogeneous_L3s" value="1"/>
1710152Satgutier@umich.edu		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
1810152Satgutier@umich.edu		<param name="homogeneous_NoCs" value="1"/>
1910152Satgutier@umich.edu		<param name="core_tech_node" value="40"/><!-- nm -->
2010152Satgutier@umich.edu		<param name="target_core_clockrate" value="2000"/><!--MHz -->
2110152Satgutier@umich.edu		<param name="temperature" value="380"/> <!-- Kelvin -->
2210152Satgutier@umich.edu		<param name="number_cache_levels" value="2"/>
2310152Satgutier@umich.edu		<param name="interconnect_projection_type" value="1"/><!--0: agressive wire technology; 1: conservative wire technology -->
2410152Satgutier@umich.edu		<param name="device_type" value="1"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->
2510152Satgutier@umich.edu		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when approperiate -->
2610152Satgutier@umich.edu		<param name="Embedded" value="1"/><!-- Embedded processor like ARM or general purpose processors?  -->
2710152Satgutier@umich.edu		<param name="machine_bits" value="32"/>
2810152Satgutier@umich.edu		<param name="virtual_address_width" value="32"/>
2910152Satgutier@umich.edu		<param name="physical_address_width" value="32"/>
3010152Satgutier@umich.edu		<param name="virtual_memory_page_size" value="4096"/>
3110152Satgutier@umich.edu		<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 
3210152Satgutier@umich.edu			default value is machine_bits, if not set --> 
3310152Satgutier@umich.edu		<stat name="total_cycles" value="100000"/>
3410152Satgutier@umich.edu		<stat name="idle_cycles" value="0"/>
3510152Satgutier@umich.edu		<stat name="busy_cycles"  value="100000"/>
3610152Satgutier@umich.edu			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 
3710152Satgutier@umich.edu			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->
3810152Satgutier@umich.edu		<!-- *********************** cores ******************* -->
3910152Satgutier@umich.edu		<component id="system.core0" name="core0">
4010152Satgutier@umich.edu			<!-- Core property -->
4110152Satgutier@umich.edu			<param name="clock_rate" value="2000"/>
4210152Satgutier@umich.edu			<!-- for cores with unknow timing, set to 0 to force off the opt flag -->
4310152Satgutier@umich.edu			<param name="opt_local" value="1"/>
4410152Satgutier@umich.edu			<param name="instruction_length" value="32"/>
4510152Satgutier@umich.edu			<param name="opcode_width" value="7"/>
4610152Satgutier@umich.edu			<param name="x86" value="0"/>
4710152Satgutier@umich.edu			<param name="micro_opcode_width" value="8"/>
4810152Satgutier@umich.edu			<param name="machine_type" value="0"/>
4910152Satgutier@umich.edu			<!-- inorder/OoO; 1 inorder; 0 OOO-->
5010152Satgutier@umich.edu			<param name="number_hardware_threads" value="1"/>
5110152Satgutier@umich.edu			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
5210152Satgutier@umich.edu			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 
5310152Satgutier@umich.edu			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 
5410152Satgutier@umich.edu			<param name="fetch_width" value="2"/>
5510152Satgutier@umich.edu			<!-- fetch_width determins the size of cachelines of L1 cache block -->
5610152Satgutier@umich.edu			<param name="number_instruction_fetch_ports" value="1"/>
5710152Satgutier@umich.edu			<param name="decode_width" value="2"/>
5810152Satgutier@umich.edu			<!-- decode_width determins the number of ports of the 
5910152Satgutier@umich.edu			renaming table (both RAM and CAM) scheme -->
6010152Satgutier@umich.edu			<param name="issue_width" value="4"/>
6110152Satgutier@umich.edu			<param name="peak_issue_width" value="7"/>
6210152Satgutier@umich.edu			<!-- issue_width determins the number of ports of Issue window and other logic 
6310152Satgutier@umich.edu			as in the complexity effective proccessors paper; issue_width==dispatch_width -->
6410152Satgutier@umich.edu			<param name="commit_width" value="4"/>
6510152Satgutier@umich.edu			<!-- commit_width determins the number of ports of register files -->
6610152Satgutier@umich.edu			<param name="fp_issue_width" value="1"/>
6710152Satgutier@umich.edu			<param name="prediction_width" value="1"/> 
6810152Satgutier@umich.edu			<!-- number of branch instructions can be predicted simultannouesl-->
6910152Satgutier@umich.edu			<!-- Current version of McPAT does not distinguish int and floating point pipelines 
7010152Satgutier@umich.edu			Theses parameters are reserved for future use.--> 
7110152Satgutier@umich.edu			<param name="pipelines_per_core" value="1,1"/>
7210152Satgutier@umich.edu			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
7310152Satgutier@umich.edu			<param name="pipeline_depth" value="8,8"/>
7410152Satgutier@umich.edu			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
7510152Satgutier@umich.edu			<!-- issue and exe unit-->
7610152Satgutier@umich.edu			<param name="ALU_per_core" value="3"/>
7710152Satgutier@umich.edu			<!-- contains an adder, a shifter, and a logical unit -->
7810152Satgutier@umich.edu			<param name="MUL_per_core" value="1"/>
7910152Satgutier@umich.edu			<!-- For MUL and Div -->
8010152Satgutier@umich.edu			<param name="FPU_per_core" value="1"/>		
8110152Satgutier@umich.edu			<!-- buffer between IF and ID stage -->
8210152Satgutier@umich.edu			<param name="instruction_buffer_size" value="32"/>
8310152Satgutier@umich.edu			<!-- buffer between ID and sche/exe stage -->
8410152Satgutier@umich.edu			<param name="decoded_stream_buffer_size" value="16"/>
8510152Satgutier@umich.edu			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
8610152Satgutier@umich.edu			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
8710152Satgutier@umich.edu			<param name="instruction_window_size" value="20"/>
8810152Satgutier@umich.edu			<param name="fp_instruction_window_size" value="15"/>
8910152Satgutier@umich.edu			<!-- Numbers need to be confirmed -->
9010152Satgutier@umich.edu			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
9110152Satgutier@umich.edu			<param name="ROB_size" value="0"/>
9210152Satgutier@umich.edu			<!-- each in-flight instruction has an entry in ROB -->
9310152Satgutier@umich.edu			<!-- registers -->
9410152Satgutier@umich.edu			<param name="archi_Regs_IRF_size" value="32"/>			
9510152Satgutier@umich.edu			<param name="archi_Regs_FRF_size" value="32"/>
9610152Satgutier@umich.edu			<!--  if OoO processor, phy_reg number is needed for renaming logic, 
9710152Satgutier@umich.edu			renaming logic is for both integer and floating point insts.  -->
9810152Satgutier@umich.edu			<param name="phy_Regs_IRF_size" value="64"/>
9910152Satgutier@umich.edu			<param name="phy_Regs_FRF_size" value="64"/>
10010152Satgutier@umich.edu			<!-- rename logic -->
10110152Satgutier@umich.edu			<param name="rename_scheme" value="0"/>
10210152Satgutier@umich.edu			<!-- can be RAM based(0) or CAM based(1) rename scheme 
10310152Satgutier@umich.edu			RAM-based scheme will have free list, status table;
10410152Satgutier@umich.edu			CAM-based scheme have the valid bit in the data field of the CAM 
10510152Satgutier@umich.edu			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
10610152Satgutier@umich.edu			Detailed RAT Implementation see TR -->
10710152Satgutier@umich.edu			<param name="register_windows_size" value="0"/>
10810152Satgutier@umich.edu			<!-- how many windows in the windowed register file, sun processors;
10910152Satgutier@umich.edu			no register windowing is used when this number is 0 -->
11010152Satgutier@umich.edu			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
11110152Satgutier@umich.edu			They will always try to exeute out-of-order though. -->
11210152Satgutier@umich.edu			<param name="LSU_order" value="inorder"/>
11310152Satgutier@umich.edu			<param name="store_buffer_size" value="4"/>
11410152Satgutier@umich.edu			<!-- By default, in-order cores do not have load buffers -->
11510152Satgutier@umich.edu			<param name="load_buffer_size" value="0"/>	
11610152Satgutier@umich.edu			<!-- number of ports refer to sustainable concurrent memory accesses --> 
11710152Satgutier@umich.edu			<param name="memory_ports" value="1"/>	
11810152Satgutier@umich.edu			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
11910152Satgutier@umich.edu			as well as the ports of Dcache which is connected to LSU -->	
12010152Satgutier@umich.edu			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->
12110152Satgutier@umich.edu			<param name="RAS_size" value="32"/>						
12210152Satgutier@umich.edu			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->
12310152Satgutier@umich.edu			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
12410152Satgutier@umich.edu			<stat name="total_instructions" value="400000"/>
12510152Satgutier@umich.edu			<stat name="int_instructions" value="200000"/>
12610152Satgutier@umich.edu			<stat name="fp_instructions" value="100000"/>
12710152Satgutier@umich.edu			<stat name="branch_instructions" value="100000"/>
12810152Satgutier@umich.edu			<stat name="branch_mispredictions" value="0"/>
12910152Satgutier@umich.edu			<stat name="load_instructions" value="0"/>
13010152Satgutier@umich.edu			<stat name="store_instructions" value="50000"/>
13110152Satgutier@umich.edu			<stat name="committed_instructions" value="400000"/>
13210152Satgutier@umich.edu			<stat name="committed_int_instructions" value="200000"/>
13310152Satgutier@umich.edu			<stat name="committed_fp_instructions" value="100000"/>
13410152Satgutier@umich.edu			<stat name="pipeline_duty_cycle" value="1"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
13510152Satgutier@umich.edu			<!-- the following cycle stats are used for heterogeneouse cores only, 
13610152Satgutier@umich.edu				please ignore them if homogeneouse cores -->
13710152Satgutier@umich.edu			<stat name="total_cycles" value="100000"/>
13810152Satgutier@umich.edu		    <stat name="idle_cycles" value="0"/>
13910152Satgutier@umich.edu		    <stat name="busy_cycles"  value="100000"/>
14010152Satgutier@umich.edu			<!-- instruction buffer stats -->
14110152Satgutier@umich.edu			<!-- ROB stats, both RS and Phy based OoOs have ROB
14210152Satgutier@umich.edu			performance simulator should capture the difference on accesses,
14310152Satgutier@umich.edu			otherwise, McPAT has to guess based on number of commited instructions. -->
14410152Satgutier@umich.edu			<stat name="ROB_reads" value="400000"/>
14510152Satgutier@umich.edu			<stat name="ROB_writes" value="400000"/>
14610152Satgutier@umich.edu			<!-- RAT accesses -->
14710152Satgutier@umich.edu			<stat name="rename_reads" value="800000"/> <!--lookup in renaming logic -->
14810152Satgutier@umich.edu			<stat name="rename_writes" value="400000"/><!--update dest regs. renaming logic -->
14910152Satgutier@umich.edu			<stat name="fp_rename_reads" value="200000"/>
15010152Satgutier@umich.edu			<stat name="fp_rename_writes" value="100000"/>
15110152Satgutier@umich.edu			<!-- decode and rename stage use this, should be total ic - nop -->
15210152Satgutier@umich.edu			<!-- Inst window stats -->
15310152Satgutier@umich.edu			<stat name="inst_window_reads" value="400000"/>
15410152Satgutier@umich.edu			<stat name="inst_window_writes" value="400000"/>
15510152Satgutier@umich.edu			<stat name="inst_window_wakeup_accesses" value="800000"/>
15610152Satgutier@umich.edu			<stat name="fp_inst_window_reads" value="200000"/>
15710152Satgutier@umich.edu			<stat name="fp_inst_window_writes" value="200000"/>
15810152Satgutier@umich.edu			<stat name="fp_inst_window_wakeup_accesses" value="400000"/>
15910152Satgutier@umich.edu			<!--  RF accesses -->
16010152Satgutier@umich.edu			<stat name="int_regfile_reads" value="600000"/>
16110152Satgutier@umich.edu			<stat name="float_regfile_reads" value="100000"/>
16210152Satgutier@umich.edu			<stat name="int_regfile_writes" value="300000"/>
16310152Satgutier@umich.edu			<stat name="float_regfile_writes" value="50000"/>
16410152Satgutier@umich.edu			<!-- accesses to the working reg -->
16510152Satgutier@umich.edu			<stat name="function_calls" value="5"/>
16610152Satgutier@umich.edu			<stat name="context_switches" value="260343"/>
16710152Satgutier@umich.edu			<!-- Number of Windowes switches (number of function calls and returns)-->
16810152Satgutier@umich.edu			<!-- Alu stats by default, the processor has one FPU that includes the divider and 
16910152Satgutier@umich.edu			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->
17010152Satgutier@umich.edu			<stat name="ialu_accesses" value="300000"/>			
17110152Satgutier@umich.edu			<stat name="fpu_accesses" value="100000"/>
17210152Satgutier@umich.edu			<stat name="mul_accesses" value="200000"/>
17310152Satgutier@umich.edu			<stat name="cdb_alu_accesses" value="300000"/>
17410152Satgutier@umich.edu			<stat name="cdb_mul_accesses" value="200000"/>
17510152Satgutier@umich.edu			<stat name="cdb_fpu_accesses" value="100000"/>
17610152Satgutier@umich.edu			<!-- multiple cycle accesses should be counted multiple times, 
17710152Satgutier@umich.edu			otherwise, McPAT can use internal counter for different floating point instructions 
17810152Satgutier@umich.edu			to get final accesses. But that needs detailed info for floating point inst mix -->
17910152Satgutier@umich.edu			<!--  currently the performance simulator should 
18010152Satgutier@umich.edu			make sure all the numbers are final numbers, 
18110152Satgutier@umich.edu			including the explicit read/write accesses, 
18210152Satgutier@umich.edu			and the implicite accesses such as replacements and etc.
18310152Satgutier@umich.edu			Future versions of McPAT may be able to reason the implicite access
18410152Satgutier@umich.edu			based on param and stats of last level cache
18510152Satgutier@umich.edu			The same rule applies to all cache access stats too!  -->
18610152Satgutier@umich.edu			<!-- following is AF for max power computation. 
18710152Satgutier@umich.edu				Do not change them, unless you understand them-->
18810152Satgutier@umich.edu			<stat name="IFU_duty_cycle" value="1"/>			
18910152Satgutier@umich.edu			<stat name="LSU_duty_cycle" value="0.5"/>
19010152Satgutier@umich.edu			<stat name="MemManU_I_duty_cycle" value="1"/>
19110152Satgutier@umich.edu			<stat name="MemManU_D_duty_cycle" value="0.5"/>
19210152Satgutier@umich.edu			<stat name="ALU_duty_cycle" value="1"/>
19310152Satgutier@umich.edu			<stat name="MUL_duty_cycle" value="0.3"/>
19410152Satgutier@umich.edu			<stat name="FPU_duty_cycle" value="0.3"/>
19510152Satgutier@umich.edu			<stat name="ALU_cdb_duty_cycle" value="1"/>
19610152Satgutier@umich.edu			<stat name="MUL_cdb_duty_cycle" value="0.3"/>
19710152Satgutier@umich.edu			<stat name="FPU_cdb_duty_cycle" value="0.3"/>
19810152Satgutier@umich.edu			<param name="number_of_BPT" value="2"/>
19910152Satgutier@umich.edu			<component id="system.core0.predictor" name="PBT">
20010152Satgutier@umich.edu				<!-- branch predictor; tournament predictor see Alpha implementation -->
20110152Satgutier@umich.edu				<param name="local_predictor_size" value="10,3"/>
20210152Satgutier@umich.edu				<param name="local_predictor_entries" value="1024"/>
20310152Satgutier@umich.edu				<param name="global_predictor_entries" value="4096"/>
20410152Satgutier@umich.edu				<param name="global_predictor_bits" value="2"/>
20510152Satgutier@umich.edu				<param name="chooser_predictor_entries" value="4096"/>
20610152Satgutier@umich.edu				<param name="chooser_predictor_bits" value="2"/>
20710152Satgutier@umich.edu				<!-- These parameters can be combined like below in next version
20810152Satgutier@umich.edu				<param name="load_predictor" value="10,3,1024"/>
20910152Satgutier@umich.edu				<param name="global_predictor" value="4096,2"/>
21010152Satgutier@umich.edu				<param name="predictor_chooser" value="4096,2"/>
21110152Satgutier@umich.edu				-->
21210152Satgutier@umich.edu			</component>
21310152Satgutier@umich.edu			<component id="system.core0.itlb" name="itlb">
21410152Satgutier@umich.edu				<param name="number_entries" value="64"/>
21510152Satgutier@umich.edu				<stat name="total_accesses" value="200000"/>
21610152Satgutier@umich.edu				<stat name="total_misses" value="4"/>
21710152Satgutier@umich.edu				<stat name="conflicts" value="0"/>	
21810152Satgutier@umich.edu				<!-- there is no write requests to itlb although writes happen to itlb after miss, 
21910152Satgutier@umich.edu				which is actually a replacement -->
22010152Satgutier@umich.edu			</component>
22110152Satgutier@umich.edu			<component id="system.core0.icache" name="icache">
22210152Satgutier@umich.edu				<!-- there is no write requests to itlb although writes happen to it after miss, 
22310152Satgutier@umich.edu				which is actually a replacement -->
22410152Satgutier@umich.edu				<param name="icache_config" value="32768,8,4,1,10,10,32,0"/>
22510152Satgutier@umich.edu				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy,  -->
22610152Satgutier@umich.edu				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
22710152Satgutier@umich.edu				<param name="buffer_sizes" value="4, 4, 4,0"/>
22810152Satgutier@umich.edu				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 
22910152Satgutier@umich.edu				<stat name="read_accesses" value="200000"/>
23010152Satgutier@umich.edu				<stat name="read_misses" value="0"/>
23110152Satgutier@umich.edu				<stat name="conflicts" value="0"/>				
23210152Satgutier@umich.edu			</component>
23310152Satgutier@umich.edu			<component id="system.core0.dtlb" name="dtlb">
23410152Satgutier@umich.edu				<param name="number_entries" value="64"/><!--dual threads-->
23510152Satgutier@umich.edu				<stat name="total_accesses" value="400000"/>
23610152Satgutier@umich.edu				<stat name="total_misses" value="4"/>
23710152Satgutier@umich.edu				<stat name="conflicts" value="0"/>	
23810152Satgutier@umich.edu			</component>
23910152Satgutier@umich.edu			<component id="system.core0.dcache" name="dcache">
24010152Satgutier@umich.edu			        <!-- all the buffer related are optional -->
24110152Satgutier@umich.edu				<param name="dcache_config" value="32768,8,4,1, 10,10, 32,1 "/>
24210152Satgutier@umich.edu				<param name="buffer_sizes" value="4, 4, 4, 4"/>
24310152Satgutier@umich.edu				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
24410152Satgutier@umich.edu				<stat name="read_accesses" value="800000"/>
24510152Satgutier@umich.edu				<stat name="write_accesses" value="27276"/>
24610152Satgutier@umich.edu				<stat name="read_misses" value="1632"/>
24710152Satgutier@umich.edu				<stat name="write_misses" value="183"/>
24810152Satgutier@umich.edu				<stat name="conflicts" value="0"/>	
24910152Satgutier@umich.edu			</component>
25010152Satgutier@umich.edu			<param name="number_of_BTB" value="2"/>
25110152Satgutier@umich.edu			<component id="system.core0.BTB" name="BTB">
25210152Satgutier@umich.edu			        <!-- all the buffer related are optional -->
25310152Satgutier@umich.edu				<param name="BTB_config" value="2048,4,2, 2, 1,3"/> <!--should be 4096 + 1024 -->
25410152Satgutier@umich.edu				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
25510152Satgutier@umich.edu				<stat name="read_accesses" value="400000"/> <!--See IFU code for guideline -->
25610152Satgutier@umich.edu				<stat name="write_accesses" value="0"/>
25710152Satgutier@umich.edu			</component>
25810152Satgutier@umich.edu	</component>
25910152Satgutier@umich.edu		<component id="system.L1Directory0" name="L1Directory0">
26010152Satgutier@umich.edu				<param name="Directory_type" value="0"/>
26110152Satgutier@umich.edu			    <!--0 cam based shadowed tag. 1 directory cache -->	
26210152Satgutier@umich.edu				<param name="Dir_config" value="2048,1,0,1, 4, 4, 8"/>
26310152Satgutier@umich.edu				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
26410152Satgutier@umich.edu			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
26510152Satgutier@umich.edu				<!-- all the buffer related are optional -->
26610152Satgutier@umich.edu			    <param name="clockrate" value="2000"/>
26710152Satgutier@umich.edu				<param name="ports" value="1,1,1"/>
26810152Satgutier@umich.edu				<!-- number of r, w, and rw search ports -->
26910152Satgutier@umich.edu				<param name="device_type" value="0"/>
27010152Satgutier@umich.edu				<!-- altough there are multiple access types, 
27110152Satgutier@umich.edu				Performance simulator needs to cast them into reads or writes
27210152Satgutier@umich.edu				e.g. the invalidates can be considered as writes -->
27310152Satgutier@umich.edu				<stat name="read_accesses" value="800000"/>
27410152Satgutier@umich.edu				<stat name="write_accesses" value="27276"/>
27510152Satgutier@umich.edu				<stat name="read_misses" value="1632"/>
27610152Satgutier@umich.edu				<stat name="write_misses" value="183"/>
27710152Satgutier@umich.edu				<stat name="conflicts" value="20"/>	
27810152Satgutier@umich.edu			    <stat name="duty_cycle" value="0.1"/>
27910152Satgutier@umich.edu		</component>
28010152Satgutier@umich.edu		<component id="system.L2Directory0" name="L2Directory0">
28110152Satgutier@umich.edu				<param name="Directory_type" value="1"/>
28210152Satgutier@umich.edu			    <!--0 cam based shadowed tag. 1 directory cache -->	
28310152Satgutier@umich.edu				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>
28410152Satgutier@umich.edu				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
28510152Satgutier@umich.edu			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	
28610152Satgutier@umich.edu				<!-- all the buffer related are optional -->
28710152Satgutier@umich.edu			    <param name="clockrate" value="2000"/>
28810152Satgutier@umich.edu				<param name="ports" value="1,1,1"/>
28910152Satgutier@umich.edu				<!-- number of r, w, and rw search ports -->
29010152Satgutier@umich.edu				<param name="device_type" value="0"/>
29110152Satgutier@umich.edu				<!-- altough there are multiple access types, 
29210152Satgutier@umich.edu				Performance simulator needs to cast them into reads or writes
29310152Satgutier@umich.edu				e.g. the invalidates can be considered as writes -->
29410152Satgutier@umich.edu				<stat name="read_accesses" value="58824"/>
29510152Satgutier@umich.edu				<stat name="write_accesses" value="27276"/>
29610152Satgutier@umich.edu				<stat name="read_misses" value="1632"/>
29710152Satgutier@umich.edu				<stat name="write_misses" value="183"/>
29810152Satgutier@umich.edu				<stat name="conflicts" value="100"/>	
29910152Satgutier@umich.edu		</component>
30010152Satgutier@umich.edu		<component id="system.L20" name="L20">
30110152Satgutier@umich.edu			<!-- all the buffer related are optional -->
30210152Satgutier@umich.edu				<param name="L2_config" value="1048576,32, 8, 8, 8, 23, 32, 1"/> 
30310152Satgutier@umich.edu				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
30410152Satgutier@umich.edu				<param name="buffer_sizes" value="16, 16, 16, 16"/>
30510152Satgutier@umich.edu				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
30610152Satgutier@umich.edu				<param name="clockrate" value="2000"/>
30710152Satgutier@umich.edu				<param name="ports" value="1,1,1"/>
30810152Satgutier@umich.edu				<!-- number of r, w, and rw ports -->
30910152Satgutier@umich.edu				<param name="device_type" value="0"/>
31010152Satgutier@umich.edu				<stat name="read_accesses" value="200000"/>
31110152Satgutier@umich.edu				<stat name="write_accesses" value="27276"/>
31210152Satgutier@umich.edu				<stat name="read_misses" value="1632"/>
31310152Satgutier@umich.edu				<stat name="write_misses" value="183"/>
31410152Satgutier@umich.edu				<stat name="conflicts" value="0"/>	
31510152Satgutier@umich.edu			    <stat name="duty_cycle" value="1.0"/>	
31610152Satgutier@umich.edu		</component>
31710152Satgutier@umich.edu		
31810152Satgutier@umich.edu<!--**********************************************************************-->
31910152Satgutier@umich.edu<component id="system.L30" name="L30">
32010152Satgutier@umich.edu				<param name="L3_config" value="16777216,64,16, 16, 16, 100,1"/>
32110152Satgutier@umich.edu				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
32210152Satgutier@umich.edu				<param name="clockrate" value="800"/>
32310152Satgutier@umich.edu				<param name="ports" value="1,1,1"/>
32410152Satgutier@umich.edu				<!-- number of r, w, and rw ports -->
32510152Satgutier@umich.edu				<param name="device_type" value="0"/>
32610152Satgutier@umich.edu				<param name="buffer_sizes" value="16, 16, 16, 16"/>
32710152Satgutier@umich.edu				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	
32810152Satgutier@umich.edu				<stat name="read_accesses" value="11824"/>
32910152Satgutier@umich.edu				<stat name="write_accesses" value="11276"/>
33010152Satgutier@umich.edu				<stat name="read_misses" value="1632"/>
33110152Satgutier@umich.edu				<stat name="write_misses" value="183"/>
33210152Satgutier@umich.edu				<stat name="conflicts" value="0"/>	
33310152Satgutier@umich.edu				<stat name="duty_cycle" value="1.0"/>	
33410152Satgutier@umich.edu		</component>
33510152Satgutier@umich.edu<!--**********************************************************************-->
33610152Satgutier@umich.edu		<component id="system.NoC0" name="noc0">
33710152Satgutier@umich.edu			<param name="clockrate" value="2000"/>
33810152Satgutier@umich.edu			<param name="type" value="0"/>
33910152Satgutier@umich.edu			<!--0:bus, 1:NoC , for bus no matter how many nodes sharing the bus
34010152Satgutier@umich.edu				at each time only one node can send req -->
34110152Satgutier@umich.edu			<param name="horizontal_nodes" value="1"/>
34210152Satgutier@umich.edu			<param name="vertical_nodes" value="1"/>
34310152Satgutier@umich.edu			<param name="has_global_link" value="0"/>
34410152Satgutier@umich.edu			<!-- 1 has global link, 0 does not have global link -->
34510152Satgutier@umich.edu			<param name="link_throughput" value="1"/><!--w.r.t clock -->
34610152Satgutier@umich.edu			<param name="link_latency" value="1"/><!--w.r.t clock -->
34710152Satgutier@umich.edu			<!-- througput >= latency -->
34810152Satgutier@umich.edu			<!-- Router architecture -->
34910152Satgutier@umich.edu			<param name="input_ports" value="1"/>
35010152Satgutier@umich.edu			<param name="output_ports" value="1"/>
35110152Satgutier@umich.edu			<!-- For bus the I/O ports should be 1 -->
35210152Satgutier@umich.edu			<param name="flit_bits" value="128"/>
35310152Satgutier@umich.edu			<param name="chip_coverage" value="1"/>
35410152Satgutier@umich.edu			<!-- When multiple NOC present, one NOC will cover part of the whole chip. 
35510152Satgutier@umich.edu				chip_coverage <=1 -->
35610152Satgutier@umich.edu			<param name="link_routing_over_percentage" value="0.5"/>
35710152Satgutier@umich.edu			<!-- Links can route over other components or occupy whole area.
35810152Satgutier@umich.edu				by default, 50% of the NoC global links routes over other 
35910152Satgutier@umich.edu				components -->
36010152Satgutier@umich.edu			<stat name="total_accesses" value="100000"/>
36110152Satgutier@umich.edu			<!-- This is the number of total accesses within the whole network not for each router -->
36210152Satgutier@umich.edu			<stat name="duty_cycle" value="1"/>
36310152Satgutier@umich.edu		</component>		
36410152Satgutier@umich.edu<!--**********************************************************************-->
36510152Satgutier@umich.edu		<component id="system.mem" name="mem">
36610152Satgutier@umich.edu			<!-- Main memory property -->
36710152Satgutier@umich.edu			<param name="mem_tech_node" value="32"/>
36810152Satgutier@umich.edu			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
36910152Satgutier@umich.edu			<param name="peak_transfer_rate" value="6400"/><!--MB/S-->
37010152Satgutier@umich.edu			<param name="internal_prefetch_of_DRAM_chip" value="4"/>
37110152Satgutier@umich.edu			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
37210152Satgutier@umich.edu			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
37310152Satgutier@umich.edu			<!-- above numbers can be easily found from Wikipedia -->
37410152Satgutier@umich.edu			<param name="capacity_per_channel" value="4096"/> <!-- MB -->
37510152Satgutier@umich.edu			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
37610152Satgutier@umich.edu			Current McPAT assumes single DIMMs are used.--> 		
37710152Satgutier@umich.edu			<param name="number_ranks" value="2"/>
37810152Satgutier@umich.edu			<param name="num_banks_of_DRAM_chip" value="8"/>			
37910152Satgutier@umich.edu			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
38010152Satgutier@umich.edu			<param name="output_width_of_DRAM_chip" value="8"/>
38110152Satgutier@umich.edu			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
38210152Satgutier@umich.edu			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
38310152Satgutier@umich.edu			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
38410152Satgutier@umich.edu			<param name="burstlength_of_DRAM_chip" value="8"/>
38510152Satgutier@umich.edu			<stat name="memory_accesses" value="1052"/>
38610152Satgutier@umich.edu			<stat name="memory_reads" value="1052"/>
38710152Satgutier@umich.edu			<stat name="memory_writes" value="1052"/>									
38810152Satgutier@umich.edu		</component>
38910152Satgutier@umich.edu		<component id="system.mc" name="mc">
39010152Satgutier@umich.edu			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->
39110152Satgutier@umich.edu			<!-- current version of McPAT uses published values for base parameters of memory controller
39210152Satgutier@umich.edu			improvments on MC will be added in later versions. -->
39310152Satgutier@umich.edu			<param name="mc_clock" value="400"/><!--MHz-->
39410152Satgutier@umich.edu			<param name="peak_transfer_rate" value="6400"/><!--MB/S-->
39510152Satgutier@umich.edu			<param name="llc_line_length" value="64"/><!--B-->
39610152Satgutier@umich.edu			<param name="number_mcs" value="0"/>
39710152Satgutier@umich.edu			<!-- current McPAT only supports homogeneous memory controllers -->
39810152Satgutier@umich.edu			<param name="memory_channels_per_mc" value="1"/>
39910152Satgutier@umich.edu			<param name="number_ranks" value="2"/>
40010152Satgutier@umich.edu			<!-- # of ranks of each channel-->
40110152Satgutier@umich.edu			<param name="req_window_size_per_channel" value="32"/>
40210152Satgutier@umich.edu			<param name="IO_buffer_size_per_channel" value="32"/>
40310152Satgutier@umich.edu			<param name="databus_width" value="128"/>
40410152Satgutier@umich.edu			<param name="addressbus_width" value="51"/>
40510152Satgutier@umich.edu			<!-- McPAT will add the control bus width to the addressbus width automatically -->
40610152Satgutier@umich.edu			<stat name="memory_accesses" value="66666"/>
40710152Satgutier@umich.edu			<stat name="memory_reads" value="33333"/>
40810152Satgutier@umich.edu			<stat name="memory_writes" value="33333"/>
40910152Satgutier@umich.edu			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 
41010152Satgutier@umich.edu			the average power per MC or per channel. This is sufficent for most application. 
41110152Satgutier@umich.edu			Further trackdown can be easily added in later versions. -->  			
41210152Satgutier@umich.edu		</component>
41310152Satgutier@umich.edu<!--**********************************************************************-->
41410152Satgutier@umich.edu	</component>
41510152Satgutier@umich.edu</component>
416