DFFRAM.cc revision 10448
110448Snilay@cs.wisc.edu/* Copyright (c) 2012 Massachusetts Institute of Technology 210448Snilay@cs.wisc.edu * 310448Snilay@cs.wisc.edu * Permission is hereby granted, free of charge, to any person obtaining a copy 410448Snilay@cs.wisc.edu * of this software and associated documentation files (the "Software"), to deal 510448Snilay@cs.wisc.edu * in the Software without restriction, including without limitation the rights 610448Snilay@cs.wisc.edu * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 710448Snilay@cs.wisc.edu * copies of the Software, and to permit persons to whom the Software is 810448Snilay@cs.wisc.edu * furnished to do so, subject to the following conditions: 910448Snilay@cs.wisc.edu * 1010448Snilay@cs.wisc.edu * The above copyright notice and this permission notice shall be included in 1110448Snilay@cs.wisc.edu * all copies or substantial portions of the Software. 1210448Snilay@cs.wisc.edu * 1310448Snilay@cs.wisc.edu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1410448Snilay@cs.wisc.edu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1510448Snilay@cs.wisc.edu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 1610448Snilay@cs.wisc.edu * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1710448Snilay@cs.wisc.edu * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 1810448Snilay@cs.wisc.edu * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 1910448Snilay@cs.wisc.edu * THE SOFTWARE. 2010448Snilay@cs.wisc.edu */ 2110448Snilay@cs.wisc.edu 2210447Snilay@cs.wisc.edu#include "model/electrical/DFFRAM.h" 2310447Snilay@cs.wisc.edu 2410447Snilay@cs.wisc.edu#include <cmath> 2510447Snilay@cs.wisc.edu 2610447Snilay@cs.wisc.edu#include "model/PortInfo.h" 2710447Snilay@cs.wisc.edu#include "model/EventInfo.h" 2810447Snilay@cs.wisc.edu#include "model/TransitionInfo.h" 2910447Snilay@cs.wisc.edu#include "model/timing_graph/ElectricalDriverMultiplier.h" 3010447Snilay@cs.wisc.edu#include "model/timing_graph/ElectricalNet.h" 3110447Snilay@cs.wisc.edu#include "model/std_cells/StdCell.h" 3210447Snilay@cs.wisc.edu#include "model/std_cells/StdCellLib.h" 3310447Snilay@cs.wisc.edu#include "model/electrical/Decoder.h" 3410447Snilay@cs.wisc.edu#include "model/electrical/Multiplexer.h" 3510447Snilay@cs.wisc.edu 3610447Snilay@cs.wisc.edunamespace DSENT 3710447Snilay@cs.wisc.edu{ 3810447Snilay@cs.wisc.edu using std::ceil; 3910447Snilay@cs.wisc.edu 4010447Snilay@cs.wisc.edu DFFRAM::DFFRAM(const String& instance_name_, const TechModel* tech_model_) 4110447Snilay@cs.wisc.edu : ElectricalModel(instance_name_, tech_model_) 4210447Snilay@cs.wisc.edu { 4310447Snilay@cs.wisc.edu initParameters(); 4410447Snilay@cs.wisc.edu initProperties(); 4510447Snilay@cs.wisc.edu } 4610447Snilay@cs.wisc.edu 4710447Snilay@cs.wisc.edu DFFRAM::~DFFRAM() 4810447Snilay@cs.wisc.edu {} 4910447Snilay@cs.wisc.edu 5010447Snilay@cs.wisc.edu void DFFRAM::initParameters() 5110447Snilay@cs.wisc.edu { 5210447Snilay@cs.wisc.edu addParameterName("NumberEntries"); 5310447Snilay@cs.wisc.edu addParameterName("NumberBits"); 5410447Snilay@cs.wisc.edu return; 5510447Snilay@cs.wisc.edu } 5610447Snilay@cs.wisc.edu 5710447Snilay@cs.wisc.edu void DFFRAM::initProperties() 5810447Snilay@cs.wisc.edu { 5910447Snilay@cs.wisc.edu return; 6010447Snilay@cs.wisc.edu } 6110447Snilay@cs.wisc.edu 6210447Snilay@cs.wisc.edu DFFRAM* DFFRAM::clone() const 6310447Snilay@cs.wisc.edu { 6410447Snilay@cs.wisc.edu // TODO 6510447Snilay@cs.wisc.edu return NULL; 6610447Snilay@cs.wisc.edu } 6710447Snilay@cs.wisc.edu 6810447Snilay@cs.wisc.edu void DFFRAM::constructModel() 6910447Snilay@cs.wisc.edu { 7010447Snilay@cs.wisc.edu // Get parameters 7110447Snilay@cs.wisc.edu unsigned int number_bits = getParameter("NumberBits").toUInt(); 7210447Snilay@cs.wisc.edu unsigned int number_entries = getParameter("NumberEntries").toUInt(); 7310447Snilay@cs.wisc.edu 7410447Snilay@cs.wisc.edu ASSERT(number_bits > 0, "[Error] " + getInstanceName() + 7510447Snilay@cs.wisc.edu " -> Number of bits must be > 0!"); 7610447Snilay@cs.wisc.edu ASSERT(number_entries > 0, "[Error] " + getInstanceName() + 7710447Snilay@cs.wisc.edu " -> Number of entries must be > 0!"); 7810447Snilay@cs.wisc.edu 7910447Snilay@cs.wisc.edu unsigned int number_addr_bits = (unsigned int)ceil(log2(number_entries)); 8010447Snilay@cs.wisc.edu 8110447Snilay@cs.wisc.edu // Create ports 8210447Snilay@cs.wisc.edu createInputPort("In", makeNetIndex(0, number_bits-1)); 8310447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 8410447Snilay@cs.wisc.edu { 8510447Snilay@cs.wisc.edu createInputPort("WRAddr" + (String)i); 8610447Snilay@cs.wisc.edu createInputPort("RDAddr" + (String)i); 8710447Snilay@cs.wisc.edu } 8810447Snilay@cs.wisc.edu createInputPort("WE"); 8910447Snilay@cs.wisc.edu createInputPort("CK"); 9010447Snilay@cs.wisc.edu createOutputPort("Out", makeNetIndex(0, number_bits-1)); 9110447Snilay@cs.wisc.edu 9210447Snilay@cs.wisc.edu // Create energy, power, and area results 9310447Snilay@cs.wisc.edu createElectricalResults(); 9410447Snilay@cs.wisc.edu getEventInfo("Idle")->setStaticTransitionInfos(); 9510447Snilay@cs.wisc.edu getEventInfo("Idle")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0)); 9610447Snilay@cs.wisc.edu getEventInfo("Idle")->setTransitionInfo("WE", TransitionInfo(1.0, 0.0, 0.0)); 9710447Snilay@cs.wisc.edu 9810447Snilay@cs.wisc.edu createElectricalEventResult("Read"); 9910447Snilay@cs.wisc.edu getEventInfo("Read")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0)); 10010447Snilay@cs.wisc.edu getEventInfo("Read")->setTransitionInfo("WE", TransitionInfo(1.0, 0.0, 0.0)); 10110447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 10210447Snilay@cs.wisc.edu { 10310447Snilay@cs.wisc.edu getEventInfo("Read")->setTransitionInfo("WRAddr" + (String)i, TransitionInfo(0.5, 0.0, 0.5)); 10410447Snilay@cs.wisc.edu } 10510447Snilay@cs.wisc.edu createElectricalEventResult("Write"); 10610447Snilay@cs.wisc.edu getEventInfo("Write")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0)); 10710447Snilay@cs.wisc.edu getEventInfo("Write")->setTransitionInfo("WE", TransitionInfo(0.0, 0.0, 1.0)); 10810447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 10910447Snilay@cs.wisc.edu { 11010447Snilay@cs.wisc.edu getEventInfo("Write")->setTransitionInfo("RDAddr" + (String)i, TransitionInfo(0.5, 0.0, 0.5)); 11110447Snilay@cs.wisc.edu } 11210447Snilay@cs.wisc.edu 11310447Snilay@cs.wisc.edu // Init components - DFF array, Dec, Mux 11410447Snilay@cs.wisc.edu vector<String> dff_names(number_entries, ""); 11510447Snilay@cs.wisc.edu vector<StdCell*> dffs(number_entries, NULL); 11610447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 11710447Snilay@cs.wisc.edu { 11810447Snilay@cs.wisc.edu dff_names[i] = "DFF_" + (String)i; 11910447Snilay@cs.wisc.edu dffs[i] = getTechModel()->getStdCellLib()->createStdCell("DFFQ", dff_names[i]); 12010447Snilay@cs.wisc.edu dffs[i]->construct(); 12110447Snilay@cs.wisc.edu } 12210447Snilay@cs.wisc.edu 12310447Snilay@cs.wisc.edu const String& dec_name = "Dec"; 12410447Snilay@cs.wisc.edu Decoder* dec = new Decoder(dec_name, getTechModel()); 12510447Snilay@cs.wisc.edu dec->setParameter("NumberOutputs", number_entries); 12610447Snilay@cs.wisc.edu dec->construct(); 12710447Snilay@cs.wisc.edu 12810447Snilay@cs.wisc.edu const String& mux_name = "Mux"; 12910447Snilay@cs.wisc.edu Multiplexer* mux = new Multiplexer(mux_name, getTechModel()); 13010447Snilay@cs.wisc.edu mux->setParameter("NumberInputs", number_entries); 13110447Snilay@cs.wisc.edu mux->setParameter("NumberBits", 1); 13210447Snilay@cs.wisc.edu mux->setParameter("BitDuplicate", "TRUE"); 13310447Snilay@cs.wisc.edu mux->construct(); 13410447Snilay@cs.wisc.edu 13510447Snilay@cs.wisc.edu // Init components - CK & WE 13610447Snilay@cs.wisc.edu const String& nand2cg0_name = "NAND2_CKGate0"; 13710447Snilay@cs.wisc.edu StdCell* nand2cg0 = getTechModel()->getStdCellLib()->createStdCell("NAND2", nand2cg0_name); 13810447Snilay@cs.wisc.edu nand2cg0->construct(); 13910447Snilay@cs.wisc.edu const String& invcg0_name = "INV_CKGate0"; 14010447Snilay@cs.wisc.edu StdCell* invcg0 = getTechModel()->getStdCellLib()->createStdCell("INV", invcg0_name); 14110447Snilay@cs.wisc.edu invcg0->construct(); 14210447Snilay@cs.wisc.edu 14310447Snilay@cs.wisc.edu // Init components - (CK & WE) & DecOut[i] 14410447Snilay@cs.wisc.edu vector<String> nand2cg1_names(number_entries, ""); 14510447Snilay@cs.wisc.edu vector<StdCell*> nand2cg1s(number_entries, NULL); 14610447Snilay@cs.wisc.edu vector<String> invcg1_names(number_entries, ""); 14710447Snilay@cs.wisc.edu vector<StdCell*> invcg1s(number_entries, NULL); 14810447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 14910447Snilay@cs.wisc.edu { 15010447Snilay@cs.wisc.edu nand2cg1_names[i] = "NAND2_CKGate1_" + (String)i; 15110447Snilay@cs.wisc.edu nand2cg1s[i] = getTechModel()->getStdCellLib()->createStdCell("NAND2", nand2cg1_names[i]); 15210447Snilay@cs.wisc.edu nand2cg1s[i]->construct(); 15310447Snilay@cs.wisc.edu 15410447Snilay@cs.wisc.edu invcg1_names[i] = "INV_CKGate1_" + (String)i; 15510447Snilay@cs.wisc.edu invcg1s[i] = getTechModel()->getStdCellLib()->createStdCell("INV", invcg1_names[i]); 15610447Snilay@cs.wisc.edu invcg1s[i]->construct(); 15710447Snilay@cs.wisc.edu } 15810447Snilay@cs.wisc.edu 15910447Snilay@cs.wisc.edu // Connect Decoder 16010447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 16110447Snilay@cs.wisc.edu { 16210447Snilay@cs.wisc.edu portConnect(dec, "Addr" + (String)i, "WRAddr" + (String)i); 16310447Snilay@cs.wisc.edu } 16410447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 16510447Snilay@cs.wisc.edu { 16610447Snilay@cs.wisc.edu createNet("Dec_Out" + (String)i); 16710447Snilay@cs.wisc.edu portConnect(dec, "Out" + (String)i, "Dec_Out" + (String)i); 16810447Snilay@cs.wisc.edu } 16910447Snilay@cs.wisc.edu 17010447Snilay@cs.wisc.edu // Connect CKGate0 - CK, WE 17110447Snilay@cs.wisc.edu createNet("NAND2_CKGate0_Out"); 17210447Snilay@cs.wisc.edu createNet("CKGate0_Out"); 17310447Snilay@cs.wisc.edu portConnect(nand2cg0, "A", "CK"); 17410447Snilay@cs.wisc.edu portConnect(nand2cg0, "B", "WE"); 17510447Snilay@cs.wisc.edu portConnect(nand2cg0, "Y", "NAND2_CKGate0_Out"); 17610447Snilay@cs.wisc.edu portConnect(invcg0, "A", "NAND2_CKGate0_Out"); 17710447Snilay@cs.wisc.edu portConnect(invcg0, "Y", "CKGate0_Out"); 17810447Snilay@cs.wisc.edu 17910447Snilay@cs.wisc.edu // Connect CKGate1 - CKGate0, Dec_Out 18010447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 18110447Snilay@cs.wisc.edu { 18210447Snilay@cs.wisc.edu createNet("NAND2_CKGate1_Outs" + (String)i); 18310447Snilay@cs.wisc.edu createNet("CKGate1_Outs" + (String)i); 18410447Snilay@cs.wisc.edu portConnect(nand2cg1s[i], "A", "CKGate0_Out"); 18510447Snilay@cs.wisc.edu portConnect(nand2cg1s[i], "B", "Dec_Out" + (String)i); 18610447Snilay@cs.wisc.edu portConnect(nand2cg1s[i], "Y", "NAND2_CKGate1_Outs" + (String)i); 18710447Snilay@cs.wisc.edu portConnect(invcg1s[i], "A", "NAND2_CKGate1_Outs" + (String)i); 18810447Snilay@cs.wisc.edu portConnect(invcg1s[i], "Y", "CKGate1_Outs" + (String)i); 18910447Snilay@cs.wisc.edu } 19010447Snilay@cs.wisc.edu 19110447Snilay@cs.wisc.edu // Connect DFF array 19210447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 19310447Snilay@cs.wisc.edu { 19410447Snilay@cs.wisc.edu createNet("DFF_Out" + (String)i); 19510447Snilay@cs.wisc.edu for(unsigned int n = 0; n < number_bits; ++n) 19610447Snilay@cs.wisc.edu { 19710447Snilay@cs.wisc.edu portConnect(dffs[i], "D", "In", makeNetIndex(n)); 19810447Snilay@cs.wisc.edu portConnect(dffs[i], "CK", "CKGate1_Outs" + (String)i); 19910447Snilay@cs.wisc.edu } 20010447Snilay@cs.wisc.edu portConnect(dffs[i], "Q", "DFF_Out" + (String)i); 20110447Snilay@cs.wisc.edu } 20210447Snilay@cs.wisc.edu 20310447Snilay@cs.wisc.edu // Connect Multiplexer 20410447Snilay@cs.wisc.edu createNet("Mux_Out"); 20510447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 20610447Snilay@cs.wisc.edu { 20710447Snilay@cs.wisc.edu portConnect(mux, "In" + (String)i, "DFF_Out" + (String)i); 20810447Snilay@cs.wisc.edu } 20910447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 21010447Snilay@cs.wisc.edu { 21110447Snilay@cs.wisc.edu portConnect(mux, "Sel" + (String)i, "RDAddr" + (String)i); 21210447Snilay@cs.wisc.edu } 21310447Snilay@cs.wisc.edu portConnect(mux, "Out", "Mux_Out"); 21410447Snilay@cs.wisc.edu 21510447Snilay@cs.wisc.edu // Use driver multiplier to connect Mux_Out to Out 21610447Snilay@cs.wisc.edu createDriverMultiplier("OutMult"); 21710447Snilay@cs.wisc.edu ElectricalDriverMultiplier* drive_mult = getDriverMultiplier("OutMult"); 21810447Snilay@cs.wisc.edu getNet("Mux_Out")->addDownstreamNode(drive_mult); 21910447Snilay@cs.wisc.edu for(unsigned int n = 0; n < number_bits; ++n) 22010447Snilay@cs.wisc.edu { 22110447Snilay@cs.wisc.edu drive_mult->addDownstreamNode(getNet("Out", makeNetIndex(n))); 22210447Snilay@cs.wisc.edu } 22310447Snilay@cs.wisc.edu 22410447Snilay@cs.wisc.edu // Add area and power results 22510447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 22610447Snilay@cs.wisc.edu { 22710447Snilay@cs.wisc.edu addSubInstances(dffs[i], number_bits); 22810447Snilay@cs.wisc.edu addElectricalSubResults(dffs[i], number_bits); 22910447Snilay@cs.wisc.edu } 23010447Snilay@cs.wisc.edu 23110447Snilay@cs.wisc.edu addSubInstances(dec, 1.0); 23210447Snilay@cs.wisc.edu addElectricalSubResults(dec, 1.0); 23310447Snilay@cs.wisc.edu 23410447Snilay@cs.wisc.edu addSubInstances(mux, number_bits); 23510447Snilay@cs.wisc.edu addElectricalSubResults(mux, number_bits); 23610447Snilay@cs.wisc.edu 23710447Snilay@cs.wisc.edu addSubInstances(nand2cg0, 1.0); 23810447Snilay@cs.wisc.edu addElectricalSubResults(nand2cg0, 1.0); 23910447Snilay@cs.wisc.edu 24010447Snilay@cs.wisc.edu addSubInstances(invcg0, 1); 24110447Snilay@cs.wisc.edu addElectricalSubResults(invcg0, 1.0); 24210447Snilay@cs.wisc.edu 24310447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 24410447Snilay@cs.wisc.edu { 24510447Snilay@cs.wisc.edu addSubInstances(nand2cg1s[i], 1); 24610447Snilay@cs.wisc.edu addElectricalSubResults(nand2cg1s[i], 1.0); 24710447Snilay@cs.wisc.edu 24810447Snilay@cs.wisc.edu addSubInstances(invcg1s[i], 1); 24910447Snilay@cs.wisc.edu addElectricalSubResults(invcg1s[i], 1.0); 25010447Snilay@cs.wisc.edu } 25110447Snilay@cs.wisc.edu 25210447Snilay@cs.wisc.edu // Add write event 25310447Snilay@cs.wisc.edu Result* write_event = getEventResult("Write"); 25410447Snilay@cs.wisc.edu write_event->addSubResult(nand2cg0->getEventResult("NAND2"), nand2cg0_name, 1.0); 25510447Snilay@cs.wisc.edu write_event->addSubResult(invcg0->getEventResult("INV"), invcg0_name, 1.0); 25610447Snilay@cs.wisc.edu write_event->addSubResult(dec->getEventResult("Decode"), dec_name, 1.0); 25710447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 25810447Snilay@cs.wisc.edu { 25910447Snilay@cs.wisc.edu write_event->addSubResult(nand2cg1s[i]->getEventResult("NAND2"), nand2cg1_names[i], 1.0); 26010447Snilay@cs.wisc.edu write_event->addSubResult(invcg1s[i]->getEventResult("INV"), invcg1_names[i], 1.0); 26110447Snilay@cs.wisc.edu write_event->addSubResult(dffs[i]->getEventResult("DFFD"), dff_names[i], number_bits); 26210447Snilay@cs.wisc.edu write_event->addSubResult(dffs[i]->getEventResult("DFFQ"), dff_names[i], number_bits); 26310447Snilay@cs.wisc.edu write_event->addSubResult(dffs[i]->getEventResult("CK"), dff_names[i], number_bits); 26410447Snilay@cs.wisc.edu } 26510447Snilay@cs.wisc.edu 26610447Snilay@cs.wisc.edu // Add read event 26710447Snilay@cs.wisc.edu Result* read_event = getEventResult("Read"); 26810447Snilay@cs.wisc.edu //for(unsigned int i = 0; i < number_entries; ++i) 26910447Snilay@cs.wisc.edu //{ 27010447Snilay@cs.wisc.edu // read_event->addSubResult(dffs[i]->getEventResult("DFFQ"), dff_names[i], number_bits); 27110447Snilay@cs.wisc.edu //} 27210447Snilay@cs.wisc.edu read_event->addSubResult(mux->getEventResult("Mux"), mux_name, number_bits); 27310447Snilay@cs.wisc.edu 27410447Snilay@cs.wisc.edu return; 27510447Snilay@cs.wisc.edu } 27610447Snilay@cs.wisc.edu 27710447Snilay@cs.wisc.edu void DFFRAM::propagateTransitionInfo() 27810447Snilay@cs.wisc.edu { 27910447Snilay@cs.wisc.edu // Update probability 28010447Snilay@cs.wisc.edu unsigned int number_entries = (unsigned int)getParameter("NumberEntries"); 28110447Snilay@cs.wisc.edu unsigned int number_addr_bits = (unsigned int)ceil(log2(number_entries)); 28210447Snilay@cs.wisc.edu 28310447Snilay@cs.wisc.edu // Update decoder 28410447Snilay@cs.wisc.edu ElectricalModel* dec = (ElectricalModel*)getSubInstance("Dec"); 28510447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 28610447Snilay@cs.wisc.edu { 28710447Snilay@cs.wisc.edu propagatePortTransitionInfo(dec, "Addr" + (String)i, "WRAddr" + (String)i); 28810447Snilay@cs.wisc.edu } 28910447Snilay@cs.wisc.edu dec->use(); 29010447Snilay@cs.wisc.edu 29110447Snilay@cs.wisc.edu // Update CKGate0 nands + invs 29210447Snilay@cs.wisc.edu ElectricalModel* nand2cg0 = (ElectricalModel*)getSubInstance("NAND2_CKGate0"); 29310447Snilay@cs.wisc.edu propagatePortTransitionInfo(nand2cg0, "A", "CK"); 29410447Snilay@cs.wisc.edu propagatePortTransitionInfo(nand2cg0, "B", "WE"); 29510447Snilay@cs.wisc.edu nand2cg0->use(); 29610447Snilay@cs.wisc.edu ElectricalModel* invcg0 = (ElectricalModel*)getSubInstance("INV_CKGate0"); 29710447Snilay@cs.wisc.edu propagatePortTransitionInfo(invcg0, "A", nand2cg0, "Y"); 29810447Snilay@cs.wisc.edu invcg0->use(); 29910447Snilay@cs.wisc.edu 30010447Snilay@cs.wisc.edu // Update CKGate1 nands + invs 30110447Snilay@cs.wisc.edu vector<ElectricalModel*> nand2cg1s(number_entries, NULL); 30210447Snilay@cs.wisc.edu vector<ElectricalModel*> invcg1s(number_entries, NULL); 30310447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 30410447Snilay@cs.wisc.edu { 30510447Snilay@cs.wisc.edu nand2cg1s[i] = (ElectricalModel*)getSubInstance("NAND2_CKGate1_" + (String)i); 30610447Snilay@cs.wisc.edu propagatePortTransitionInfo(nand2cg1s[i], "A", invcg0, "Y"); 30710447Snilay@cs.wisc.edu propagatePortTransitionInfo(nand2cg1s[i], "B", dec, "Out" + (String)i); 30810447Snilay@cs.wisc.edu nand2cg1s[i]->use(); 30910447Snilay@cs.wisc.edu 31010447Snilay@cs.wisc.edu invcg1s[i] = (ElectricalModel*)getSubInstance("INV_CKGate1_" + (String)i); 31110447Snilay@cs.wisc.edu propagatePortTransitionInfo(invcg1s[i], "A", nand2cg1s[i], "Y"); 31210447Snilay@cs.wisc.edu invcg1s[i]->use(); 31310447Snilay@cs.wisc.edu } 31410447Snilay@cs.wisc.edu 31510447Snilay@cs.wisc.edu // Update DFF 31610447Snilay@cs.wisc.edu vector<ElectricalModel*> dffs(number_entries, NULL); 31710447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 31810447Snilay@cs.wisc.edu { 31910447Snilay@cs.wisc.edu dffs[i] = (ElectricalModel*)getSubInstance("DFF_" + (String)i); 32010447Snilay@cs.wisc.edu propagatePortTransitionInfo(dffs[i], "D", "In"); 32110447Snilay@cs.wisc.edu propagatePortTransitionInfo(dffs[i], "CK", invcg1s[i], "Y"); 32210447Snilay@cs.wisc.edu dffs[i]->use(); 32310447Snilay@cs.wisc.edu } 32410447Snilay@cs.wisc.edu 32510447Snilay@cs.wisc.edu // Update Mux 32610447Snilay@cs.wisc.edu ElectricalModel* mux = (ElectricalModel*)getSubInstance("Mux"); 32710447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_entries; ++i) 32810447Snilay@cs.wisc.edu { 32910447Snilay@cs.wisc.edu propagatePortTransitionInfo(mux, "In" + (String)i, dffs[i], "Q"); 33010447Snilay@cs.wisc.edu } 33110447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 33210447Snilay@cs.wisc.edu { 33310447Snilay@cs.wisc.edu propagatePortTransitionInfo(mux, "Sel" + (String)i, "RDAddr" + (String)i); 33410447Snilay@cs.wisc.edu } 33510447Snilay@cs.wisc.edu mux->use(); 33610447Snilay@cs.wisc.edu 33710447Snilay@cs.wisc.edu // Set output probability 33810447Snilay@cs.wisc.edu getOutputPort("Out")->setTransitionInfo(mux->getOutputPort("Out")->getTransitionInfo()); 33910447Snilay@cs.wisc.edu return; 34010447Snilay@cs.wisc.edu } 34110447Snilay@cs.wisc.edu} // namespace DSENT 34210447Snilay@cs.wisc.edu 343