110447Snilay@cs.wisc.edu
210447Snilay@cs.wisc.edu# Name of model to be built and evaluated
310447Snilay@cs.wisc.eduModelName                               = Router
410447Snilay@cs.wisc.edu
510447Snilay@cs.wisc.edu# Query string to choose what to evaluate (use '\' to enable multiline config)
610447Snilay@cs.wisc.eduQueryString                             = \
710447Snilay@cs.wisc.edu    Energy>>Router:WriteBuffer@0 \
810447Snilay@cs.wisc.edu    Energy>>Router:ReadBuffer@0 \
910447Snilay@cs.wisc.edu    Energy>>Router:TraverseCrossbar->Multicast1@0 \
1010447Snilay@cs.wisc.edu    Energy>>Router:ArbitrateSwitch->ArbitrateStage1@0 \
1110447Snilay@cs.wisc.edu    Energy>>Router:ArbitrateSwitch->ArbitrateStage2@0 \
1210447Snilay@cs.wisc.edu    Energy>>Router:DistributeClock@0 \
1310447Snilay@cs.wisc.edu    NddPower>>Router:Leakage@1 \
1410447Snilay@cs.wisc.edu    Area>>Router:Active@1 \
1510447Snilay@cs.wisc.edu
1610447Snilay@cs.wisc.edu
1710447Snilay@cs.wisc.edu# Injection rate (# flits per cycle per port), assuming that the router is not
1810447Snilay@cs.wisc.edu# saturated
1910447Snilay@cs.wisc.eduInjectionRate                           = 0.3
2010447Snilay@cs.wisc.edu# Evaluation string
2110447Snilay@cs.wisc.eduEvaluateString                          = \
2210447Snilay@cs.wisc.edu    ejection_rate   = $(NumberInputPorts) * $(InjectionRate) / $(NumberOutputPorts); \
2310447Snilay@cs.wisc.edu    buf_rd_dynamic  = $(Energy>>Router:ReadBuffer) * $(Frequency); \
2410447Snilay@cs.wisc.edu    buf_wr_dynamic  = $(Energy>>Router:WriteBuffer) * $(Frequency); \
2510447Snilay@cs.wisc.edu    buf_static      = $(NddPower>>Router->InputPort:Leakage) * $(NumberInputPorts) + ($(NddPower>>Router->PipelineReg0:Leakage) + $(NddPower>>Router->PipelineReg1:Leakage)) * $(NumberInputPorts) * $(NumberBitsPerFlit); \
2610447Snilay@cs.wisc.edu    xbar_o_dynamic  = $(Energy>>Router:TraverseCrossbar->Multicast1) * $(Frequency); \
2710447Snilay@cs.wisc.edu    xbar_static     = $(NddPower>>Router->Crossbar:Leakage) + $(NddPower>>Router->PipelineReg2_0:Leakage) * $(NumberOutputPorts) * $(NumberBitsPerFlit); \
2810447Snilay@cs.wisc.edu    sa_o_dynamic    = ($(Energy>>Router:ArbitrateSwitch->ArbitrateStage1) + $(Energy>>Router:ArbitrateSwitch->ArbitrateStage2)) * $(Frequency); \
2910447Snilay@cs.wisc.edu    sa_static       = $(NddPower>>Router->SwitchAllocator:Leakage); \
3010447Snilay@cs.wisc.edu    clock_o_dynamic = $(Energy>>Router:DistributeClock) * $(Frequency); \
3110447Snilay@cs.wisc.edu    clock_static    = $(NddPower>>Router->ClockTree:Leakage); \
3210447Snilay@cs.wisc.edu    buffer_dynamic  = buf_wr_dynamic * $(InjectionRate) * $(NumberInputPorts) + buf_rd_dynamic * ejection_rate * $(NumberOutputPorts); \
3310447Snilay@cs.wisc.edu    buffer_leakage  = buf_static; \
3410447Snilay@cs.wisc.edu    xbar_dynamic    = xbar_o_dynamic * ejection_rate * $(NumberOutputPorts); \
3510447Snilay@cs.wisc.edu    xbar_leakage    = xbar_static; \
3610447Snilay@cs.wisc.edu    sa_dynamic      = sa_o_dynamic * ejection_rate * $(NumberOutputPorts); \
3710447Snilay@cs.wisc.edu    sa_leakage      = sa_static; \
3810447Snilay@cs.wisc.edu    clock_dynamic   = clock_o_dynamic; \
3910447Snilay@cs.wisc.edu    clock_leakage   = clock_static; \
4010447Snilay@cs.wisc.edu    total_dynamic   = buffer_dynamic + xbar_dynamic + sa_dynamic + clock_dynamic; \
4110447Snilay@cs.wisc.edu    total_leakage   = buffer_leakage + xbar_leakage + sa_leakage + clock_leakage; \
4210447Snilay@cs.wisc.edu    buf_area        = ($(Area>>Router->InputPort:Active) + ($(Area>>Router->PipelineReg0:Active) + $(Area>>Router->PipelineReg1:Active)) * $(NumberBitsPerFlit)) * $(NumberInputPorts); \
4310447Snilay@cs.wisc.edu    xbar_area       = $(Area>>Router->Crossbar:Active) + $(Area>>Router->Crossbar_Sel_DFF:Active) + $(Area>>Router->PipelineReg2_0:Active) * $(NumberBitsPerFlit) * $(NumberOutputPorts); \
4410447Snilay@cs.wisc.edu    sa_area         = $(Area>>Router->SwitchAllocator:Active); \
4510447Snilay@cs.wisc.edu    other_area      = $(Area>>Router->ClockTree:Active); \
4610447Snilay@cs.wisc.edu    print "Buffer:"; \
4710447Snilay@cs.wisc.edu    print "    Dynamic power: " buffer_dynamic; \
4810447Snilay@cs.wisc.edu    print "    Leakage power: " buffer_leakage; \
4910447Snilay@cs.wisc.edu    print "Crossbar:"; \
5010447Snilay@cs.wisc.edu    print "    Dynamic power: " xbar_dynamic; \
5110447Snilay@cs.wisc.edu    print "    Leakage power: " xbar_leakage; \
5210447Snilay@cs.wisc.edu    print "Switch allocator:"; \
5310447Snilay@cs.wisc.edu    print "    Dynamic power: " sa_dynamic; \
5410447Snilay@cs.wisc.edu    print "    Leakage power: " sa_leakage; \
5510447Snilay@cs.wisc.edu    print "Clock:"; \
5610447Snilay@cs.wisc.edu    print "    Dynamic power: " clock_dynamic; \
5710447Snilay@cs.wisc.edu    print "    Leakage power: " clock_leakage; \
5810447Snilay@cs.wisc.edu    print "Total:"; \
5910447Snilay@cs.wisc.edu    print "    Dynamic power: " total_dynamic; \
6010447Snilay@cs.wisc.edu    print "    Leakage power: " $(NddPower>>Router:Leakage); \
6110447Snilay@cs.wisc.edu    print "Area:"; \
6210447Snilay@cs.wisc.edu    print "    Buffer:           " buf_area; \
6310447Snilay@cs.wisc.edu    print "    Crossbar:         " xbar_area; \
6410447Snilay@cs.wisc.edu    print "    Switch allocator: " sa_area; \
6510447Snilay@cs.wisc.edu    print "    Other:            " other_area; \
6610447Snilay@cs.wisc.edu
6710447Snilay@cs.wisc.edu# Technology file (see other models in tech/models)
6810448Snilay@cs.wisc.eduElectricalTechModelFilename             = ext/dsent/tech/tech_models/Bulk45LVT.model
6910447Snilay@cs.wisc.edu
7010447Snilay@cs.wisc.edu###############################################################################
7110447Snilay@cs.wisc.edu# Timing optimization
7210447Snilay@cs.wisc.edu###############################################################################
7310447Snilay@cs.wisc.edu
7410447Snilay@cs.wisc.edu# True if want to perform timing optimization; otherwise, false.
7510447Snilay@cs.wisc.eduIsPerformTimingOptimization             = true
7610447Snilay@cs.wisc.edu# Nets that the timing optimizer starts from
7710447Snilay@cs.wisc.eduTimingOptimization->StartNetNames       = [*]
7810447Snilay@cs.wisc.edu# Operating frequency (Hz)
7910447Snilay@cs.wisc.eduFrequency                               = 1.0e9
8010447Snilay@cs.wisc.edu
8110447Snilay@cs.wisc.edu###############################################################################
8210447Snilay@cs.wisc.edu# Model specifications
8310447Snilay@cs.wisc.edu###############################################################################
8410447Snilay@cs.wisc.edu
8510447Snilay@cs.wisc.edu# Number of input ports
8610447Snilay@cs.wisc.eduNumberInputPorts                        = 5
8710447Snilay@cs.wisc.edu# Number of output ports
8810447Snilay@cs.wisc.eduNumberOutputPorts                       = 5
8910447Snilay@cs.wisc.edu# Flit width (bit)
9010447Snilay@cs.wisc.eduNumberBitsPerFlit                       = 64
9110447Snilay@cs.wisc.edu
9210447Snilay@cs.wisc.edu# In this example, we define 2 virtual networks (message classes), VN1 and VN2. 
9310447Snilay@cs.wisc.edu#                           VN1 VN2
9410447Snilay@cs.wisc.edu# Number of VCs              2   3
9510447Snilay@cs.wisc.edu# Number of buffers / VC     4   5
9610447Snilay@cs.wisc.edu#
9710447Snilay@cs.wisc.edu# So in total, there are (2 * 4) + (3 * 5) = 23 flit buffers
9810447Snilay@cs.wisc.edu#
9910447Snilay@cs.wisc.edu# Number of virtual networks (number of message classes)
10010447Snilay@cs.wisc.eduNumberVirtualNetworks                   = 2
10110447Snilay@cs.wisc.edu# Number of virtual channels per virtual network
10210447Snilay@cs.wisc.eduNumberVirtualChannelsPerVirtualNetwork  = [2, 3]
10310447Snilay@cs.wisc.edu# Number of buffers per virtual channel
10410447Snilay@cs.wisc.eduNumberBuffersPerVirtualChannel          = [4, 5]
10510447Snilay@cs.wisc.edu
10610447Snilay@cs.wisc.edu# InputPort 
10710447Snilay@cs.wisc.edu# ---------
10810447Snilay@cs.wisc.edu# buffer model
10910447Snilay@cs.wisc.eduInputPort->BufferModel                  = DFFRAM
11010447Snilay@cs.wisc.edu
11110447Snilay@cs.wisc.edu# Crossbar
11210447Snilay@cs.wisc.edu# --------
11310447Snilay@cs.wisc.edu# crossbar model
11410447Snilay@cs.wisc.eduCrossbarModel                           = MultiplexerCrossbar
11510447Snilay@cs.wisc.edu
11610447Snilay@cs.wisc.edu# Switch allocator
11710447Snilay@cs.wisc.edu# ----------------
11810447Snilay@cs.wisc.edu# arbiter model
11910447Snilay@cs.wisc.eduSwitchAllocator->ArbiterModel           = MatrixArbiter
12010447Snilay@cs.wisc.edu
12110447Snilay@cs.wisc.edu# Clock tree
12210447Snilay@cs.wisc.edu# ----------
12310447Snilay@cs.wisc.edu# clock tree model
12410447Snilay@cs.wisc.eduClockTreeModel                          = BroadcastHTree
12510447Snilay@cs.wisc.edu# number of levels
12610447Snilay@cs.wisc.eduClockTree->NumberLevels                 = 5
12710447Snilay@cs.wisc.edu# wire layer
12810447Snilay@cs.wisc.eduClockTree->WireLayer                    = Global
12910447Snilay@cs.wisc.edu# wire width multiplier
13010447Snilay@cs.wisc.eduClockTree->WireWidthMultiplier          = 1.0
13110447Snilay@cs.wisc.edu
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