run.py revision 7525
19665Sandreas.hansson@arm.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 29665Sandreas.hansson@arm.com# All rights reserved. 39665Sandreas.hansson@arm.com# 49665Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 59665Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 69665Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 79665Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 89665Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 99665Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 109665Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 119665Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 129665Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 135353Svilas.sridharan@gmail.com# this software without specific prior written permission. 143395Shsul@eecs.umich.edu# 153395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263395Shsul@eecs.umich.edu# 273395Shsul@eecs.umich.edu# Authors: Ron Dreslinski 283395Shsul@eecs.umich.edu 293395Shsul@eecs.umich.edu# Splash2 Run Script 303395Shsul@eecs.umich.edu# 313395Shsul@eecs.umich.edu 323395Shsul@eecs.umich.eduimport os 333395Shsul@eecs.umich.eduimport optparse 343395Shsul@eecs.umich.eduimport sys 353395Shsul@eecs.umich.edu 363395Shsul@eecs.umich.eduimport m5 373395Shsul@eecs.umich.edufrom m5.objects import * 383395Shsul@eecs.umich.edu 393395Shsul@eecs.umich.edum5.util.addToPath('../common') 403395Shsul@eecs.umich.edu 418920Snilay@cs.wisc.edu# -------------------- 428920Snilay@cs.wisc.edu# Define Command Line Options 438920Snilay@cs.wisc.edu# ==================== 448920Snilay@cs.wisc.edu 457025SBrad.Beckmann@amd.comparser = optparse.OptionParser() 469520SAndreas.Sandberg@ARM.com 479665Sandreas.hansson@arm.comparser.add_option("-d", "--detailed", action="store_true") 4811238Sandreas.sandberg@arm.comparser.add_option("-t", "--timing", action="store_true") 499520SAndreas.Sandberg@ARM.comparser.add_option("-m", "--maxtick", type="int") 5010747SChris.Emmons@arm.comparser.add_option("-n", "--numcpus", 5110747SChris.Emmons@arm.com help="Number of cpus in total", type="int") 529520SAndreas.Sandberg@ARM.comparser.add_option("-f", "--frequency", 539520SAndreas.Sandberg@ARM.com default = "1GHz", 549520SAndreas.Sandberg@ARM.com help="Frequency of each CPU") 559520SAndreas.Sandberg@ARM.comparser.add_option("--l1size", 569665Sandreas.hansson@arm.com default = "32kB") 579665Sandreas.hansson@arm.comparser.add_option("--l1latency", 589665Sandreas.hansson@arm.com default = "1ns") 599665Sandreas.hansson@arm.comparser.add_option("--l2size", 6011238Sandreas.sandberg@arm.com default = "256kB") 6111238Sandreas.sandberg@arm.comparser.add_option("--l2latency", 6211238Sandreas.sandberg@arm.com default = "10ns") 6311238Sandreas.sandberg@arm.comparser.add_option("--rootdir", 648920Snilay@cs.wisc.edu help="Root directory of Splash2", 658920Snilay@cs.wisc.edu default="/dist/splash2/codes") 669520SAndreas.Sandberg@ARM.comparser.add_option("-b", "--benchmark", 679520SAndreas.Sandberg@ARM.com help="Splash 2 benchmark to run") 689520SAndreas.Sandberg@ARM.com 698920Snilay@cs.wisc.edu(options, args) = parser.parse_args() 709520SAndreas.Sandberg@ARM.com 718920Snilay@cs.wisc.eduif args: 728920Snilay@cs.wisc.edu print "Error: script doesn't take any positional arguments" 738920Snilay@cs.wisc.edu sys.exit(1) 749827Sakash.bagdia@arm.com 759827Sakash.bagdia@arm.comif not options.numcpus: 769827Sakash.bagdia@arm.com print "Specify the number of cpus with -n" 779827Sakash.bagdia@arm.com sys.exit(1) 789790Sakash.bagdia@arm.com 799790Sakash.bagdia@arm.com# -------------------- 809790Sakash.bagdia@arm.com# Define Splash2 Benchmarks 819790Sakash.bagdia@arm.com# ==================== 829789Sakash.bagdia@arm.comclass Cholesky(LiveProcess): 839789Sakash.bagdia@arm.com cwd = options.rootdir + '/kernels/cholesky' 849789Sakash.bagdia@arm.com executable = options.rootdir + '/kernels/cholesky/CHOLESKY' 859800Snilay@cs.wisc.edu cmd = ['CHOLESKY', '-p' + str(options.numcpus), 869800Snilay@cs.wisc.edu options.rootdir + '/kernels/cholesky/inputs/tk23.O'] 879800Snilay@cs.wisc.edu 889800Snilay@cs.wisc.educlass FFT(LiveProcess): 899800Snilay@cs.wisc.edu cwd = options.rootdir + '/kernels/fft' 9011251Sradhika.jagtap@ARM.com executable = options.rootdir + '/kernels/fft/FFT' 9111251Sradhika.jagtap@ARM.com cmd = ['FFT', '-p', str(options.numcpus), '-m18'] 9211251Sradhika.jagtap@ARM.com 9311251Sradhika.jagtap@ARM.comclass LU_contig(LiveProcess): 9411251Sradhika.jagtap@ARM.com executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU' 9511251Sradhika.jagtap@ARM.com cmd = ['LU', '-p', str(options.numcpus)] 9611251Sradhika.jagtap@ARM.com cwd = options.rootdir + '/kernels/lu/contiguous_blocks' 9711251Sradhika.jagtap@ARM.com 9811251Sradhika.jagtap@ARM.comclass LU_noncontig(LiveProcess): 9911251Sradhika.jagtap@ARM.com executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU' 10011251Sradhika.jagtap@ARM.com cmd = ['LU', '-p', str(options.numcpus)] 10111251Sradhika.jagtap@ARM.com cwd = options.rootdir + '/kernels/lu/non_contiguous_blocks' 10211251Sradhika.jagtap@ARM.com 1039800Snilay@cs.wisc.educlass Radix(LiveProcess): 1049800Snilay@cs.wisc.edu executable = options.rootdir + '/kernels/radix/RADIX' 1059800Snilay@cs.wisc.edu cmd = ['RADIX', '-n524288', '-p', str(options.numcpus)] 1069800Snilay@cs.wisc.edu cwd = options.rootdir + '/kernels/radix' 1079800Snilay@cs.wisc.edu 10810789Sandreas.hansson@arm.comclass Barnes(LiveProcess): 1099800Snilay@cs.wisc.edu executable = options.rootdir + '/apps/barnes/BARNES' 1109800Snilay@cs.wisc.edu cmd = ['BARNES'] 1119836Sandreas.hansson@arm.com input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus) 1129836Sandreas.hansson@arm.com cwd = options.rootdir + '/apps/barnes' 11310620Sandreas.hansson@arm.com 11410620Sandreas.hansson@arm.comclass FMM(LiveProcess): 1159800Snilay@cs.wisc.edu executable = options.rootdir + '/apps/fmm/FMM' 1169800Snilay@cs.wisc.edu cmd = ['FMM'] 1179800Snilay@cs.wisc.edu if str(options.numcpus) == '1': 1189800Snilay@cs.wisc.edu input = options.rootdir + '/apps/fmm/inputs/input.2048' 11910037SARM gem5 Developers else: 12010037SARM gem5 Developers input = options.rootdir + '/apps/fmm/inputs/input.2048.p' + str(options.numcpus) 12110037SARM gem5 Developers cwd = options.rootdir + '/apps/fmm' 12210613SMarco.Elver@ARM.com 12310613SMarco.Elver@ARM.comclass Ocean_contig(LiveProcess): 1249800Snilay@cs.wisc.edu executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN' 12510780SCurtis.Dunham@arm.com cmd = ['OCEAN', '-p', str(options.numcpus)] 12610780SCurtis.Dunham@arm.com cwd = options.rootdir + '/apps/ocean/contiguous_partitions' 12710993Sjungma@eit.uni-kl.de 12810993Sjungma@eit.uni-kl.declass Ocean_noncontig(LiveProcess): 1299800Snilay@cs.wisc.edu executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN' 1309800Snilay@cs.wisc.edu cmd = ['OCEAN', '-p', str(options.numcpus)] 1319800Snilay@cs.wisc.edu cwd = options.rootdir + '/apps/ocean/non_contiguous_partitions' 1328920Snilay@cs.wisc.edu 1338920Snilay@cs.wisc.educlass Raytrace(LiveProcess): 1348920Snilay@cs.wisc.edu executable = options.rootdir + '/apps/raytrace/RAYTRACE' 1358920Snilay@cs.wisc.edu cmd = ['RAYTRACE', '-p' + str(options.numcpus), 1368920Snilay@cs.wisc.edu options.rootdir + '/apps/raytrace/inputs/teapot.env'] 1378920Snilay@cs.wisc.edu cwd = options.rootdir + '/apps/raytrace' 1388920Snilay@cs.wisc.edu 1398920Snilay@cs.wisc.educlass Water_nsquared(LiveProcess): 1408920Snilay@cs.wisc.edu executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED' 1418920Snilay@cs.wisc.edu cmd = ['WATER-NSQUARED'] 1428920Snilay@cs.wisc.edu if options.numcpus==1: 1438920Snilay@cs.wisc.edu input = options.rootdir + '/apps/water-nsquared/input' 1449800Snilay@cs.wisc.edu else: 14511626Smichael.lebeane@amd.com input = options.rootdir + '/apps/water-nsquared/input.p' + str(options.numcpus) 14611626Smichael.lebeane@amd.com cwd = options.rootdir + '/apps/water-nsquared' 14711626Smichael.lebeane@amd.com 14811626Smichael.lebeane@amd.comclass Water_spatial(LiveProcess): 14911626Smichael.lebeane@amd.com executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL' 15011626Smichael.lebeane@amd.com cmd = ['WATER-SPATIAL'] 15111626Smichael.lebeane@amd.com if options.numcpus==1: 15211626Smichael.lebeane@amd.com input = options.rootdir + '/apps/water-spatial/input' 15311626Smichael.lebeane@amd.com else: 15411626Smichael.lebeane@amd.com input = options.rootdir + '/apps/water-spatial/input.p' + str(options.numcpus) 15511626Smichael.lebeane@amd.com cwd = options.rootdir + '/apps/water-spatial' 15611626Smichael.lebeane@amd.com 15711626Smichael.lebeane@amd.com# -------------------- 15811626Smichael.lebeane@amd.com# Base L1 Cache Definition 15911626Smichael.lebeane@amd.com# ==================== 16011626Smichael.lebeane@amd.com 16111626Smichael.lebeane@amd.comclass L1(BaseCache): 16211626Smichael.lebeane@amd.com latency = options.l1latency 16311626Smichael.lebeane@amd.com block_size = 64 16411626Smichael.lebeane@amd.com mshrs = 12 16511626Smichael.lebeane@amd.com tgts_per_mshr = 8 16611626Smichael.lebeane@amd.com 16711626Smichael.lebeane@amd.com# ---------------------- 16811626Smichael.lebeane@amd.com# Base L2 Cache Definition 16911626Smichael.lebeane@amd.com# ---------------------- 17011626Smichael.lebeane@amd.com 17111626Smichael.lebeane@amd.comclass L2(BaseCache): 17211626Smichael.lebeane@amd.com block_size = 64 17311626Smichael.lebeane@amd.com latency = options.l2latency 17411626Smichael.lebeane@amd.com mshrs = 92 17511626Smichael.lebeane@amd.com tgts_per_mshr = 16 17611626Smichael.lebeane@amd.com write_buffers = 8 17711626Smichael.lebeane@amd.com 1789800Snilay@cs.wisc.edu# ---------------------- 1798920Snilay@cs.wisc.edu# Define the cpus 1803395Shsul@eecs.umich.edu# ---------------------- 1818920Snilay@cs.wisc.edu 1829909Snilay@cs.wisc.edubusFrequency = Frequency(options.frequency) 1839816Sjthestness@gmail.com 1849816Sjthestness@gmail.comif options.timing: 1859816Sjthestness@gmail.com cpus = [TimingSimpleCPU(cpu_id = i, 1869816Sjthestness@gmail.com clock=options.frequency) 1879816Sjthestness@gmail.com for i in xrange(options.numcpus)] 1889816Sjthestness@gmail.comelif options.detailed: 1899816Sjthestness@gmail.com cpus = [DerivO3CPU(cpu_id = i, 1909816Sjthestness@gmail.com clock=options.frequency) 1919816Sjthestness@gmail.com for i in xrange(options.numcpus)] 1928920Snilay@cs.wisc.eduelse: 1938920Snilay@cs.wisc.edu cpus = [AtomicSimpleCPU(cpu_id = i, 1948920Snilay@cs.wisc.edu clock=options.frequency) 1958920Snilay@cs.wisc.edu for i in xrange(options.numcpus)] 1968920Snilay@cs.wisc.edu 19710159Sgedare@rtems.org# ---------------------- 19810159Sgedare@rtems.org# Create a system, and add system wide objects 1998920Snilay@cs.wisc.edu# ---------------------- 2008920Snilay@cs.wisc.edusystem = System(cpu = cpus, physmem = PhysicalMemory(), 2018920Snilay@cs.wisc.edu membus = Bus(clock = busFrequency)) 2028920Snilay@cs.wisc.edu 2038920Snilay@cs.wisc.edusystem.toL2bus = Bus(clock = busFrequency) 2048920Snilay@cs.wisc.edusystem.l2 = L2(size = options.l2size, assoc = 8) 2058920Snilay@cs.wisc.edu 2068920Snilay@cs.wisc.edu# ---------------------- 2078920Snilay@cs.wisc.edu# Connect the L2 cache and memory together 20810757SCurtis.Dunham@arm.com# ---------------------- 20910757SCurtis.Dunham@arm.com 21010757SCurtis.Dunham@arm.comsystem.physmem.port = system.membus.port 2116776SBrad.Beckmann@amd.comsystem.l2.cpu_side = system.toL2bus.port 2129800Snilay@cs.wisc.edusystem.l2.mem_side = system.membus.port 2139800Snilay@cs.wisc.edu 2149800Snilay@cs.wisc.edu# ---------------------- 2159800Snilay@cs.wisc.edu# Connect the L2 cache and clusters together 2169800Snilay@cs.wisc.edu# ---------------------- 21710608Sdam.sunwoo@arm.comfor cpu in cpus: 21810608Sdam.sunwoo@arm.com cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), 21910608Sdam.sunwoo@arm.com L1(size = options.l1size, assoc = 4)) 22010608Sdam.sunwoo@arm.com cpu.mem = cpu.dcache 22110608Sdam.sunwoo@arm.com # connect cpu level-1 caches to shared level-2 cache 2229800Snilay@cs.wisc.edu cpu.connectMemPorts(system.toL2bus) 2238920Snilay@cs.wisc.edu 2248920Snilay@cs.wisc.edu 2258920Snilay@cs.wisc.edu# ---------------------- 2268920Snilay@cs.wisc.edu# Define the root 2279357Sandreas.hansson@arm.com# ---------------------- 2288920Snilay@cs.wisc.edu 2298920Snilay@cs.wisc.eduroot = Root(system = system) 2308920Snilay@cs.wisc.edu 2318920Snilay@cs.wisc.edu# -------------------- 2328920Snilay@cs.wisc.edu# Pick the correct Splash2 Benchmarks 2338920Snilay@cs.wisc.edu# ==================== 2348920Snilay@cs.wisc.eduif options.benchmark == 'Cholesky': 2358920Snilay@cs.wisc.edu root.workload = Cholesky() 2368920Snilay@cs.wisc.eduelif options.benchmark == 'FFT': 2378920Snilay@cs.wisc.edu root.workload = FFT() 2388920Snilay@cs.wisc.eduelif options.benchmark == 'LUContig': 2398920Snilay@cs.wisc.edu root.workload = LU_contig() 2408920Snilay@cs.wisc.eduelif options.benchmark == 'LUNoncontig': 2418920Snilay@cs.wisc.edu root.workload = LU_noncontig() 2428920Snilay@cs.wisc.eduelif options.benchmark == 'Radix': 2439736Sandreas@sandberg.pp.se root.workload = Radix() 2448920Snilay@cs.wisc.eduelif options.benchmark == 'Barnes': 2453395Shsul@eecs.umich.edu root.workload = Barnes() 2465361Srstrong@cs.ucsd.eduelif options.benchmark == 'FMM': 2478920Snilay@cs.wisc.edu root.workload = FMM() 2488920Snilay@cs.wisc.eduelif options.benchmark == 'OceanContig': 2498920Snilay@cs.wisc.edu root.workload = Ocean_contig() 2509151Satgutier@umich.eduelif options.benchmark == 'OceanNoncontig': 2519151Satgutier@umich.edu root.workload = Ocean_noncontig() 2529151Satgutier@umich.eduelif options.benchmark == 'Raytrace': 2539151Satgutier@umich.edu root.workload = Raytrace() 2549151Satgutier@umich.eduelif options.benchmark == 'WaterNSquared': 2559151Satgutier@umich.edu root.workload = Water_nsquared() 2569562Ssaidi@eecs.umich.eduelif options.benchmark == 'WaterSpatial': 2578920Snilay@cs.wisc.edu root.workload = Water_spatial() 2588920Snilay@cs.wisc.eduelse: 2598920Snilay@cs.wisc.edu print >> sys.stderr, """The --benchmark environment variable was set to something improper. 2608920Snilay@cs.wisc.eduUse Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig, 2618920Snilay@cs.wisc.eduOceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial""" 2628920Snilay@cs.wisc.edu sys.exit(1) 2638920Snilay@cs.wisc.edu 2648920Snilay@cs.wisc.edu# -------------------- 2658920Snilay@cs.wisc.edu# Assign the workload to the cpus 2668920Snilay@cs.wisc.edu# ==================== 2678920Snilay@cs.wisc.edu 2688920Snilay@cs.wisc.edufor cpu in cpus: 2698920Snilay@cs.wisc.edu cpu.workload = root.workload 2708920Snilay@cs.wisc.edu 2718920Snilay@cs.wisc.edu# ---------------------- 2728920Snilay@cs.wisc.edu# Run the simulation 2738920Snilay@cs.wisc.edu# ---------------------- 27410037SARM gem5 Developers 27510037SARM gem5 Developersif options.timing or options.detailed: 27610037SARM gem5 Developers root.system.mem_mode = 'timing' 27710037SARM gem5 Developers 27810037SARM gem5 Developers# instantiate configuration 27910037SARM gem5 Developersm5.instantiate() 28010037SARM gem5 Developers 28110037SARM gem5 Developers# simulate until program terminates 2828920Snilay@cs.wisc.eduif options.maxtick: 2838920Snilay@cs.wisc.edu exit_event = m5.simulate(options.maxtick) 2848920Snilay@cs.wisc.eduelse: 2858920Snilay@cs.wisc.edu exit_event = m5.simulate(m5.MaxTick) 2868920Snilay@cs.wisc.edu 2878920Snilay@cs.wisc.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 2888920Snilay@cs.wisc.edu 2898920Snilay@cs.wisc.edu