cluster.py revision 9815:3b3b94536547
19665Sandreas.hansson@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
29665Sandreas.hansson@arm.com# All rights reserved.
39665Sandreas.hansson@arm.com#
49665Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without
59665Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are
69665Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright
79665Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer;
89665Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright
99665Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the
109665Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution;
119665Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its
129665Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from
135353Svilas.sridharan@gmail.com# this software without specific prior written permission.
143395Shsul@eecs.umich.edu#
153395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
163395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
173395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
183395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
193395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
203395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
213395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
223395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
233395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
243395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
253395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
263395Shsul@eecs.umich.edu#
273395Shsul@eecs.umich.edu# Authors: Ron Dreslinski
283395Shsul@eecs.umich.edu
293395Shsul@eecs.umich.edu# Simple test script
303395Shsul@eecs.umich.edu#
313395Shsul@eecs.umich.edu# "m5 test.py"
323395Shsul@eecs.umich.edu
333395Shsul@eecs.umich.eduimport os
343395Shsul@eecs.umich.eduimport optparse
353395Shsul@eecs.umich.eduimport sys
363395Shsul@eecs.umich.edu
373395Shsul@eecs.umich.eduimport m5
383395Shsul@eecs.umich.edufrom m5.objects import *
393395Shsul@eecs.umich.edu
403395Shsul@eecs.umich.edum5.util.addToPath('../common')
418920Snilay@cs.wisc.edu
428920Snilay@cs.wisc.edu# --------------------
438920Snilay@cs.wisc.edu# Define Command Line Options
448920Snilay@cs.wisc.edu# ====================
457025SBrad.Beckmann@amd.com
469520SAndreas.Sandberg@ARM.comparser = optparse.OptionParser()
479665Sandreas.hansson@arm.com
489520SAndreas.Sandberg@ARM.comparser.add_option("-d", "--detailed", action="store_true")
499520SAndreas.Sandberg@ARM.comparser.add_option("-t", "--timing", action="store_true")
509520SAndreas.Sandberg@ARM.comparser.add_option("-m", "--maxtick", type="int")
519520SAndreas.Sandberg@ARM.comparser.add_option("-c", "--numclusters",
529520SAndreas.Sandberg@ARM.com                  help="Number of clusters", type="int")
539665Sandreas.hansson@arm.comparser.add_option("-n", "--numcpus",
549665Sandreas.hansson@arm.com                  help="Number of cpus in total", type="int")
559665Sandreas.hansson@arm.comparser.add_option("-f", "--frequency",
569665Sandreas.hansson@arm.com                  default = "1GHz",
578920Snilay@cs.wisc.edu                  help="Frequency of each CPU")
588920Snilay@cs.wisc.eduparser.add_option("--l1size",
599520SAndreas.Sandberg@ARM.com                  default = "32kB")
609520SAndreas.Sandberg@ARM.comparser.add_option("--l1latency",
619520SAndreas.Sandberg@ARM.com                  default = 1)
628920Snilay@cs.wisc.eduparser.add_option("--l2size",
639520SAndreas.Sandberg@ARM.com                  default = "256kB")
648920Snilay@cs.wisc.eduparser.add_option("--l2latency",
659665Sandreas.hansson@arm.com                  default = 10)
669665Sandreas.hansson@arm.comparser.add_option("--rootdir",
679665Sandreas.hansson@arm.com                  help="ROot directory of Splash2",
689665Sandreas.hansson@arm.com                  default="/dist/splash2/codes/")
699665Sandreas.hansson@arm.comparser.add_option("-b", "--benchmark",
709665Sandreas.hansson@arm.com                  help="Splash 2 benchmark to run")
718920Snilay@cs.wisc.edu
728920Snilay@cs.wisc.edu(options, args) = parser.parse_args()
738920Snilay@cs.wisc.edu
748920Snilay@cs.wisc.eduif args:
758920Snilay@cs.wisc.edu    print "Error: script doesn't take any positional arguments"
769647Sdam.sunwoo@arm.com    sys.exit(1)
779647Sdam.sunwoo@arm.com
789647Sdam.sunwoo@arm.com# --------------------
799647Sdam.sunwoo@arm.com# Define Splash2 Benchmarks
808920Snilay@cs.wisc.edu# ====================
818920Snilay@cs.wisc.educlass Cholesky(LiveProcess):
828920Snilay@cs.wisc.edu        executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
838920Snilay@cs.wisc.edu        cmd = 'CHOLESKY -p' + str(options.numcpus) + ' '\
848920Snilay@cs.wisc.edu             + options.rootdir + '/kernels/cholesky/inputs/tk23.O'
858920Snilay@cs.wisc.edu
868920Snilay@cs.wisc.educlass FFT(LiveProcess):
878920Snilay@cs.wisc.edu        executable = options.rootdir + 'kernels/fft/FFT'
888920Snilay@cs.wisc.edu        cmd = 'FFT -p' + str(options.numcpus) + ' -m18'
898920Snilay@cs.wisc.edu
908920Snilay@cs.wisc.educlass LU_contig(LiveProcess):
918920Snilay@cs.wisc.edu        executable = options.rootdir + 'kernels/lu/contiguous_blocks/LU'
928920Snilay@cs.wisc.edu        cmd = 'LU -p' + str(options.numcpus)
938920Snilay@cs.wisc.edu
949197Snilay@cs.wisc.educlass LU_noncontig(LiveProcess):
959197Snilay@cs.wisc.edu        executable = options.rootdir + 'kernels/lu/non_contiguous_blocks/LU'
969197Snilay@cs.wisc.edu        cmd = 'LU -p' + str(options.numcpus)
979197Snilay@cs.wisc.edu
989197Snilay@cs.wisc.educlass Radix(LiveProcess):
993395Shsul@eecs.umich.edu        executable = options.rootdir + 'kernels/radix/RADIX'
1008920Snilay@cs.wisc.edu        cmd = 'RADIX -n524288 -p' + str(options.numcpus)
1018920Snilay@cs.wisc.edu
1028920Snilay@cs.wisc.educlass Barnes(LiveProcess):
1038920Snilay@cs.wisc.edu        executable = options.rootdir + 'apps/barnes/BARNES'
1048920Snilay@cs.wisc.edu        cmd = 'BARNES'
1058920Snilay@cs.wisc.edu        input = options.rootdir + 'apps/barnes/input.p' + str(options.numcpus)
1068920Snilay@cs.wisc.edu
1078920Snilay@cs.wisc.educlass FMM(LiveProcess):
1088920Snilay@cs.wisc.edu        executable = options.rootdir + 'apps/fmm/FMM'
1098920Snilay@cs.wisc.edu        cmd = 'FMM'
1108920Snilay@cs.wisc.edu        input = options.rootdir + 'apps/fmm/inputs/input.2048.p' + str(options.numcpus)
1118920Snilay@cs.wisc.edu
1128920Snilay@cs.wisc.educlass Ocean_contig(LiveProcess):
1138920Snilay@cs.wisc.edu        executable = options.rootdir + 'apps/ocean/contiguous_partitions/OCEAN'
1148920Snilay@cs.wisc.edu        cmd = 'OCEAN -p' + str(options.numcpus)
1158920Snilay@cs.wisc.edu
1168920Snilay@cs.wisc.educlass Ocean_noncontig(LiveProcess):
1178920Snilay@cs.wisc.edu        executable = options.rootdir + 'apps/ocean/non_contiguous_partitions/OCEAN'
1186776SBrad.Beckmann@amd.com        cmd = 'OCEAN -p' + str(options.numcpus)
1198920Snilay@cs.wisc.edu
1208920Snilay@cs.wisc.educlass Raytrace(LiveProcess):
1218920Snilay@cs.wisc.edu        executable = options.rootdir + 'apps/raytrace/RAYTRACE'
1228920Snilay@cs.wisc.edu        cmd = 'RAYTRACE -p' + str(options.numcpus) + ' ' \
1239357Sandreas.hansson@arm.com             + options.rootdir + 'apps/raytrace/inputs/teapot.env'
1248920Snilay@cs.wisc.edu
1258920Snilay@cs.wisc.educlass Water_nsquared(LiveProcess):
1268920Snilay@cs.wisc.edu        executable = options.rootdir + 'apps/water-nsquared/WATER-NSQUARED'
1278920Snilay@cs.wisc.edu        cmd = 'WATER-NSQUARED'
1288920Snilay@cs.wisc.edu        input = options.rootdir + 'apps/water-nsquared/input.p' + str(options.numcpus)
1298920Snilay@cs.wisc.edu
1308920Snilay@cs.wisc.educlass Water_spatial(LiveProcess):
1318920Snilay@cs.wisc.edu        executable = options.rootdir + 'apps/water-spatial/WATER-SPATIAL'
1328920Snilay@cs.wisc.edu        cmd = 'WATER-SPATIAL'
1338920Snilay@cs.wisc.edu        input = options.rootdir + 'apps/water-spatial/input.p' + str(options.numcpus)
1348920Snilay@cs.wisc.edu
1358920Snilay@cs.wisc.edu
1368920Snilay@cs.wisc.edu# --------------------
1378920Snilay@cs.wisc.edu# Base L1 Cache Definition
1388920Snilay@cs.wisc.edu# ====================
1398920Snilay@cs.wisc.edu
1408920Snilay@cs.wisc.educlass L1(BaseCache):
1418920Snilay@cs.wisc.edu    latency = options.l1latency
1423395Shsul@eecs.umich.edu    mshrs = 12
1435361Srstrong@cs.ucsd.edu    tgts_per_mshr = 8
1448920Snilay@cs.wisc.edu
1458920Snilay@cs.wisc.edu# ----------------------
1468920Snilay@cs.wisc.edu# Base L2 Cache Definition
1479151Satgutier@umich.edu# ----------------------
1489151Satgutier@umich.edu
1499151Satgutier@umich.educlass L2(BaseCache):
1509151Satgutier@umich.edu    latency = options.l2latency
1519151Satgutier@umich.edu    mshrs = 92
1529151Satgutier@umich.edu    tgts_per_mshr = 16
1539562Ssaidi@eecs.umich.edu    write_buffers = 8
1548920Snilay@cs.wisc.edu
1558920Snilay@cs.wisc.edu# ----------------------
1568920Snilay@cs.wisc.edu# Define the clusters with their cpus
1578920Snilay@cs.wisc.edu# ----------------------
1588920Snilay@cs.wisc.educlass Cluster:
1598920Snilay@cs.wisc.edu    pass
1608920Snilay@cs.wisc.edu
1618920Snilay@cs.wisc.educpusPerCluster = options.numcpus/options.numclusters
1628920Snilay@cs.wisc.edu
1638920Snilay@cs.wisc.edubusFrequency = Frequency(options.frequency)
1648920Snilay@cs.wisc.edubusFrequency *= cpusPerCluster
1658920Snilay@cs.wisc.edu
1668920Snilay@cs.wisc.eduall_cpus = []
1678920Snilay@cs.wisc.eduall_l1s = []
1688920Snilay@cs.wisc.eduall_l1buses = []
1698920Snilay@cs.wisc.eduif options.timing:
1708920Snilay@cs.wisc.edu    clusters = [ Cluster() for i in xrange(options.numclusters)]
1718920Snilay@cs.wisc.edu    for j in xrange(options.numclusters):
1728920Snilay@cs.wisc.edu        clusters[j].id = j
1738920Snilay@cs.wisc.edu    for cluster in clusters:
1748920Snilay@cs.wisc.edu        cluster.clusterbus = CoherentBus(clock=busFrequency)
1758920Snilay@cs.wisc.edu        all_l1buses += [cluster.clusterbus]
1768920Snilay@cs.wisc.edu        cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id,
1778920Snilay@cs.wisc.edu                                        clock=options.frequency)
1788920Snilay@cs.wisc.edu                        for i in xrange(cpusPerCluster)]
1798920Snilay@cs.wisc.edu        all_cpus += cluster.cpus
1808920Snilay@cs.wisc.edu        cluster.l1 = L1(size=options.l1size, assoc = 4)
1818920Snilay@cs.wisc.edu        all_l1s += [cluster.l1]
1828920Snilay@cs.wisc.eduelif options.detailed:
1838920Snilay@cs.wisc.edu    clusters = [ Cluster() for i in xrange(options.numclusters)]
1848920Snilay@cs.wisc.edu    for j in xrange(options.numclusters):
1858920Snilay@cs.wisc.edu        clusters[j].id = j
1868920Snilay@cs.wisc.edu    for cluster in clusters:
1878920Snilay@cs.wisc.edu        cluster.clusterbus = CoherentBus(clock=busFrequency)
1888920Snilay@cs.wisc.edu        all_l1buses += [cluster.clusterbus]
1898920Snilay@cs.wisc.edu        cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id,
1908920Snilay@cs.wisc.edu                                   clock=options.frequency)
1918920Snilay@cs.wisc.edu                        for i in xrange(cpusPerCluster)]
1928920Snilay@cs.wisc.edu        all_cpus += cluster.cpus
1938920Snilay@cs.wisc.edu        cluster.l1 = L1(size=options.l1size, assoc = 4)
1948920Snilay@cs.wisc.edu        all_l1s += [cluster.l1]
1958920Snilay@cs.wisc.eduelse:
1968920Snilay@cs.wisc.edu    clusters = [ Cluster() for i in xrange(options.numclusters)]
1978920Snilay@cs.wisc.edu    for j in xrange(options.numclusters):
1988920Snilay@cs.wisc.edu        clusters[j].id = j
1998920Snilay@cs.wisc.edu    for cluster in clusters:
2008920Snilay@cs.wisc.edu        cluster.clusterbus = CoherentBus(clock=busFrequency)
2018920Snilay@cs.wisc.edu        all_l1buses += [cluster.clusterbus]
2028920Snilay@cs.wisc.edu        cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id,
2039539Satgutier@umich.edu                                        clock=options.frequency)
2049539Satgutier@umich.edu                        for i in xrange(cpusPerCluster)]
2059539Satgutier@umich.edu        all_cpus += cluster.cpus
2068920Snilay@cs.wisc.edu        cluster.l1 = L1(size=options.l1size, assoc = 4)
2078920Snilay@cs.wisc.edu        all_l1s += [cluster.l1]
2088920Snilay@cs.wisc.edu
2098920Snilay@cs.wisc.edu# ----------------------
2108920Snilay@cs.wisc.edu# Create a system, and add system wide objects
2118920Snilay@cs.wisc.edu# ----------------------
2128920Snilay@cs.wisc.edusystem = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
2138920Snilay@cs.wisc.edu                physmem = SimpleMemory(),
2148920Snilay@cs.wisc.edu                membus = CoherentBus(clock = busFrequency))
2158920Snilay@cs.wisc.edusystem.clock = '1GHz'
2168920Snilay@cs.wisc.edu
2178920Snilay@cs.wisc.edusystem.toL2bus = CoherentBus(clock = busFrequency)
2188956Sjayneel@cs.wisc.edusystem.l2 = L2(size = options.l2size, assoc = 8)
2198956Sjayneel@cs.wisc.edu
2208956Sjayneel@cs.wisc.edu# ----------------------
2218956Sjayneel@cs.wisc.edu# Connect the L2 cache and memory together
2228956Sjayneel@cs.wisc.edu# ----------------------
2238956Sjayneel@cs.wisc.edu
2248956Sjayneel@cs.wisc.edusystem.physmem.port = system.membus.master
2258976Sjayneel@cs.wisc.edusystem.l2.cpu_side = system.toL2bus.slave
226system.l2.mem_side = system.membus.master
227
228# ----------------------
229# Connect the L2 cache and clusters together
230# ----------------------
231for cluster in clusters:
232    cluster.l1.cpu_side = cluster.clusterbus.master
233    cluster.l1.mem_side = system.toL2bus.slave
234    for cpu in cluster.cpus:
235        cpu.icache_port = cluster.clusterbus.slave
236        cpu.dcache_port = cluster.clusterbus.slave
237
238# ----------------------
239# Define the root
240# ----------------------
241
242root = Root(full_system = False, system = system)
243
244# --------------------
245# Pick the correct Splash2 Benchmarks
246# ====================
247if options.benchmark == 'Cholesky':
248    root.workload = Cholesky()
249elif options.benchmark == 'FFT':
250    root.workload = FFT()
251elif options.benchmark == 'LUContig':
252    root.workload = LU_contig()
253elif options.benchmark == 'LUNoncontig':
254    root.workload = LU_noncontig()
255elif options.benchmark == 'Radix':
256    root.workload = Radix()
257elif options.benchmark == 'Barnes':
258    root.workload = Barnes()
259elif options.benchmark == 'FMM':
260    root.workload = FMM()
261elif options.benchmark == 'OceanContig':
262    root.workload = Ocean_contig()
263elif options.benchmark == 'OceanNoncontig':
264    root.workload = Ocean_noncontig()
265elif options.benchmark == 'Raytrace':
266    root.workload = Raytrace()
267elif options.benchmark == 'WaterNSquared':
268    root.workload = Water_nsquared()
269elif options.benchmark == 'WaterSpatial':
270    root.workload = Water_spatial()
271else:
272    m5.util.panic("""
273The --benchmark environment variable was set to something improper.
274Use Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig,
275OceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial
276""")
277
278# --------------------
279# Assign the workload to the cpus
280# ====================
281
282for cluster in clusters:
283    for cpu in cluster.cpus:
284        cpu.workload = root.workload
285
286# ----------------------
287# Run the simulation
288# ----------------------
289
290if options.timing or options.detailed:
291    root.system.mem_mode = 'timing'
292
293# instantiate configuration
294m5.instantiate()
295
296# simulate until program terminates
297if options.maxtick:
298    exit_event = m5.simulate(options.maxtick)
299else:
300    exit_event = m5.simulate(m5.MaxTick)
301
302print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
303
304