Ruby.py revision 8257:7226aebb77b4
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26928SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36166Ssteve.reinhardt@amd.com# All rights reserved. 46166Ssteve.reinhardt@amd.com# 56166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without 66166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are 76166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright 86166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer; 96166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright 106166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the 116166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution; 126166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its 136166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from 146166Ssteve.reinhardt@amd.com# this software without specific prior written permission. 156166Ssteve.reinhardt@amd.com# 166166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246166Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276166Ssteve.reinhardt@amd.com# 286166Ssteve.reinhardt@amd.com# Authors: Brad Beckmann 296166Ssteve.reinhardt@amd.com 306166Ssteve.reinhardt@amd.comimport math 316166Ssteve.reinhardt@amd.comimport m5 326919SBrad.Beckmann@amd.comfrom m5.objects import * 336919SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 346919SBrad.Beckmann@amd.com 356166Ssteve.reinhardt@amd.comdef define_options(parser): 3611670Sandreas.hansson@arm.com # ruby network options 376919SBrad.Beckmann@amd.com parser.add_option("--topology", type="string", default="Crossbar", 3811670Sandreas.hansson@arm.com help="check src/mem/ruby/network/topologies for complete set") 3911682Sandreas.hansson@arm.com parser.add_option("--mesh-rows", type="int", default=1, 406919SBrad.Beckmann@amd.com help="the number of rows in the mesh topology") 416919SBrad.Beckmann@amd.com parser.add_option("--garnet-network", type="string", default=None, 428920Snilay@cs.wisc.edu help="'fixed'|'flexible'") 436919SBrad.Beckmann@amd.com 447570SBrad.Beckmann@amd.com # ruby mapping options 457570SBrad.Beckmann@amd.com parser.add_option("--numa-high-bit", type="int", default=0, 466919SBrad.Beckmann@amd.com help="high order address bit to use for numa mapping. " \ 476919SBrad.Beckmann@amd.com "0 = highest bit, not specified = lowest bit") 486166Ssteve.reinhardt@amd.com 497570SBrad.Beckmann@amd.com # ruby sparse memory options 507570SBrad.Beckmann@amd.com parser.add_option("--use-map", action="store_true", default=False) 517570SBrad.Beckmann@amd.com parser.add_option("--map-levels", type="int", default=4) 527570SBrad.Beckmann@amd.com 537570SBrad.Beckmann@amd.com parser.add_option("--recycle-latency", type="int", default=10, 547570SBrad.Beckmann@amd.com help="Recycle latency for ruby controller input buffers") 557570SBrad.Beckmann@amd.com 567570SBrad.Beckmann@amd.com parser.add_option("--random_seed", type="int", default=1234, 577570SBrad.Beckmann@amd.com help="Used for seeding the random number generator") 587570SBrad.Beckmann@amd.com 597570SBrad.Beckmann@amd.com protocol = buildEnv['PROTOCOL'] 607570SBrad.Beckmann@amd.com exec "import %s" % protocol 619841Snilay@cs.wisc.edu eval("%s.define_options(parser)" % protocol) 627570SBrad.Beckmann@amd.com 636166Ssteve.reinhardt@amd.comdef create_system(options, system, piobus = None, dma_devices = []): 646166Ssteve.reinhardt@amd.com 656928SBrad.Beckmann@amd.com protocol = buildEnv['PROTOCOL'] 666928SBrad.Beckmann@amd.com exec "import %s" % protocol 6710688Sandreas.hansson@arm.com try: 688436SBrad.Beckmann@amd.com (cpu_sequencers, dir_cntrls, all_cntrls) = \ 696928SBrad.Beckmann@amd.com eval("%s.create_system(options, system, piobus, dma_devices)" \ 706166Ssteve.reinhardt@amd.com % protocol) 716919SBrad.Beckmann@amd.com except: 726919SBrad.Beckmann@amd.com print "Error: could not create sytem for ruby protocol %s" % protocol 7311320Ssteve.reinhardt@amd.com raise 746919SBrad.Beckmann@amd.com 7510688Sandreas.hansson@arm.com # 769827Sakash.bagdia@arm.com # Set the network classes based on the command line options 779827Sakash.bagdia@arm.com # 789827Sakash.bagdia@arm.com if options.garnet_network == "fixed": 799827Sakash.bagdia@arm.com class NetworkClass(GarnetNetwork_d): pass 809793Sakash.bagdia@arm.com class IntLinkClass(GarnetIntLink_d): pass 819793Sakash.bagdia@arm.com class ExtLinkClass(GarnetExtLink_d): pass 829793Sakash.bagdia@arm.com class RouterClass(GarnetRouter_d): pass 839827Sakash.bagdia@arm.com elif options.garnet_network == "flexible": 849827Sakash.bagdia@arm.com class NetworkClass(GarnetNetwork): pass 859793Sakash.bagdia@arm.com class IntLinkClass(GarnetIntLink): pass 869793Sakash.bagdia@arm.com class ExtLinkClass(GarnetExtLink): pass 879793Sakash.bagdia@arm.com class RouterClass(GarnetRouter): pass 889793Sakash.bagdia@arm.com else: 896289Snate@binkert.org class NetworkClass(SimpleNetwork): pass 909826Sandreas.hansson@arm.com class IntLinkClass(BasicIntLink): pass 919826Sandreas.hansson@arm.com class ExtLinkClass(BasicExtLink): pass 9210519Snilay@cs.wisc.edu class RouterClass(BasicRouter): pass 936166Ssteve.reinhardt@amd.com 949793Sakash.bagdia@arm.com # 959827Sakash.bagdia@arm.com # Important: the topology must be created before the network and after the 969827Sakash.bagdia@arm.com # controllers. 979793Sakash.bagdia@arm.com # 9810120Snilay@cs.wisc.edu exec "import %s" % options.topology 996166Ssteve.reinhardt@amd.com try: 10010120Snilay@cs.wisc.edu net_topology = eval("%s.makeTopology(all_cntrls, options, \ 1016919SBrad.Beckmann@amd.com IntLinkClass, ExtLinkClass, \ 10210688Sandreas.hansson@arm.com RouterClass)" \ 1036919SBrad.Beckmann@amd.com % options.topology) 1046919SBrad.Beckmann@amd.com except: 10510688Sandreas.hansson@arm.com print "Error: could not create topology %s" % options.topology 10610688Sandreas.hansson@arm.com raise 1077938SBrad.Beckmann@amd.com 1087938SBrad.Beckmann@amd.com network = NetworkClass(topology = net_topology) 1097938SBrad.Beckmann@amd.com 1107938SBrad.Beckmann@amd.com # 1117938SBrad.Beckmann@amd.com # Loop through the directory controlers. 1126166Ssteve.reinhardt@amd.com # Determine the total memory size of the ruby system and verify it is equal 1136166Ssteve.reinhardt@amd.com # to physmem. However, if Ruby memory is using sparse memory in SE 1146166Ssteve.reinhardt@amd.com # mode, then the system should not back-up the memory state with 1156166Ssteve.reinhardt@amd.com # the Memory Vector and thus the memory size bytes should stay at 0. 1166166Ssteve.reinhardt@amd.com # Also set the numa bits to the appropriate values. 1178801Sgblack@eecs.umich.edu # 1186166Ssteve.reinhardt@amd.com total_mem_size = MemorySize('0B') 1196928SBrad.Beckmann@amd.com 1206928SBrad.Beckmann@amd.com dir_bits = int(math.log(options.num_dirs, 2)) 1216928SBrad.Beckmann@amd.com 122 if options.numa_high_bit: 123 numa_bit = options.numa_high_bit 124 else: 125 # if not specified, use the lowest bits above the block offest 126 if dir_bits > 0: 127 # add 5 because bits 0-5 are the block offset 128 numa_bit = dir_bits + 5 129 else: 130 numa_bit = 6 131 132 for dir_cntrl in dir_cntrls: 133 total_mem_size.value += dir_cntrl.directory.size.value 134 dir_cntrl.directory.numa_high_bit = numa_bit 135 136 physmem_size = long(system.physmem.range.second) - \ 137 long(system.physmem.range.first) + 1 138 assert(total_mem_size.value == physmem_size) 139 140 ruby_profiler = RubyProfiler(num_of_sequencers = len(cpu_sequencers)) 141 142 ruby = RubySystem(clock = options.clock, 143 network = network, 144 profiler = ruby_profiler, 145 tracer = RubyTracer(), 146 mem_size = total_mem_size) 147 148 ruby.cpu_ruby_ports = cpu_sequencers 149 ruby.random_seed = options.random_seed 150 151 return ruby 152