Ruby.py revision 14038:8ba13d8b7810
111723Sar4jc@virginia.edu# Copyright (c) 2012, 2017-2018 ARM Limited 211723Sar4jc@virginia.edu# All rights reserved. 311723Sar4jc@virginia.edu# 411723Sar4jc@virginia.edu# The license below extends only to copyright in the software and shall 511723Sar4jc@virginia.edu# not be construed as granting a license to any other intellectual 611723Sar4jc@virginia.edu# property including but not limited to intellectual property relating 711723Sar4jc@virginia.edu# to a hardware implementation of the functionality of the software 811723Sar4jc@virginia.edu# licensed hereunder. You may use the software subject to the license 911723Sar4jc@virginia.edu# terms below provided that you ensure that this notice is replicated 1011723Sar4jc@virginia.edu# unmodified and in its entirety in all distributions of the software, 1111723Sar4jc@virginia.edu# modified or unmodified, in source code or in binary form. 1211723Sar4jc@virginia.edu# 1311723Sar4jc@virginia.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 1411723Sar4jc@virginia.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 1511723Sar4jc@virginia.edu# All rights reserved. 1611723Sar4jc@virginia.edu# 1711723Sar4jc@virginia.edu# Redistribution and use in source and binary forms, with or without 1811723Sar4jc@virginia.edu# modification, are permitted provided that the following conditions are 1911723Sar4jc@virginia.edu# met: redistributions of source code must retain the above copyright 2011723Sar4jc@virginia.edu# notice, this list of conditions and the following disclaimer; 2111723Sar4jc@virginia.edu# redistributions in binary form must reproduce the above copyright 2211723Sar4jc@virginia.edu# notice, this list of conditions and the following disclaimer in the 2311723Sar4jc@virginia.edu# documentation and/or other materials provided with the distribution; 2411723Sar4jc@virginia.edu# neither the name of the copyright holders nor the names of its 2511723Sar4jc@virginia.edu# contributors may be used to endorse or promote products derived from 2611723Sar4jc@virginia.edu# this software without specific prior written permission. 2711723Sar4jc@virginia.edu# 2811723Sar4jc@virginia.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911723Sar4jc@virginia.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011723Sar4jc@virginia.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111723Sar4jc@virginia.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211723Sar4jc@virginia.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311723Sar4jc@virginia.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411723Sar4jc@virginia.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511723Sar4jc@virginia.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611723Sar4jc@virginia.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711723Sar4jc@virginia.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811723Sar4jc@virginia.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911723Sar4jc@virginia.edu# 4011723Sar4jc@virginia.edu# Authors: Brad Beckmann 4111723Sar4jc@virginia.edu 4211723Sar4jc@virginia.edufrom __future__ import print_function 4311723Sar4jc@virginia.edu 4411723Sar4jc@virginia.eduimport math 4511723Sar4jc@virginia.eduimport m5 4611723Sar4jc@virginia.edufrom m5.objects import * 4711723Sar4jc@virginia.edufrom m5.defines import buildEnv 4811723Sar4jc@virginia.edufrom m5.util import addToPath, fatal 4911723Sar4jc@virginia.edu 5011723Sar4jc@virginia.eduaddToPath('../') 5111723Sar4jc@virginia.edu 5211723Sar4jc@virginia.edufrom common import MemConfig 5311723Sar4jc@virginia.edufrom common import FileSystemConfig 5411723Sar4jc@virginia.edu 5511723Sar4jc@virginia.edufrom topologies import * 5611723Sar4jc@virginia.edufrom network import Network 5711723Sar4jc@virginia.edu 5811723Sar4jc@virginia.edudef define_options(parser): 5911723Sar4jc@virginia.edu # By default, ruby uses the simple timing cpu 6011723Sar4jc@virginia.edu parser.set_defaults(cpu_type="TimingSimpleCPU") 6111723Sar4jc@virginia.edu 6211723Sar4jc@virginia.edu parser.add_option("--ruby-clock", action="store", type="string", 6311723Sar4jc@virginia.edu default='2GHz', 6411723Sar4jc@virginia.edu help="Clock for blocks running at Ruby system's speed") 6511723Sar4jc@virginia.edu 6611723Sar4jc@virginia.edu parser.add_option("--access-backing-store", action="store_true", default=False, 6712136Sar4jc@virginia.edu help="Should ruby maintain a second copy of memory") 6812136Sar4jc@virginia.edu 6912136Sar4jc@virginia.edu # Options related to cache structure 7012136Sar4jc@virginia.edu parser.add_option("--ports", action="store", type="int", default=4, 7112136Sar4jc@virginia.edu help="used of transitions per cycle which is a proxy \ 7212136Sar4jc@virginia.edu for the number of ports.") 7312136Sar4jc@virginia.edu 7411723Sar4jc@virginia.edu # network options are in network/Network.py 7511723Sar4jc@virginia.edu 7611723Sar4jc@virginia.edu # ruby mapping options 7711723Sar4jc@virginia.edu parser.add_option("--numa-high-bit", type="int", default=0, 7811723Sar4jc@virginia.edu help="high order address bit to use for numa mapping. " \ 7911723Sar4jc@virginia.edu "0 = highest bit, not specified = lowest bit") 8011723Sar4jc@virginia.edu 8111723Sar4jc@virginia.edu parser.add_option("--recycle-latency", type="int", default=10, 8211725Sar4jc@virginia.edu help="Recycle latency for ruby controller input buffers") 8311725Sar4jc@virginia.edu 8411725Sar4jc@virginia.edu protocol = buildEnv['PROTOCOL'] 8511725Sar4jc@virginia.edu exec("from . import %s" % protocol) 8611725Sar4jc@virginia.edu eval("%s.define_options(parser)" % protocol) 8711725Sar4jc@virginia.edu Network.define_options(parser) 8811725Sar4jc@virginia.edu 8911723Sar4jc@virginia.edudef setup_memory_controllers(system, ruby, dir_cntrls, options): 9011723Sar4jc@virginia.edu ruby.block_size_bytes = options.cacheline_size 9111723Sar4jc@virginia.edu ruby.memory_size_bits = 48 9211723Sar4jc@virginia.edu 9311723Sar4jc@virginia.edu index = 0 9411723Sar4jc@virginia.edu mem_ctrls = [] 9511723Sar4jc@virginia.edu crossbars = [] 9611723Sar4jc@virginia.edu 9711877Sbrandon.potter@amd.com if options.numa_high_bit: 9811877Sbrandon.potter@amd.com dir_bits = int(math.log(options.num_dirs, 2)) 9911723Sar4jc@virginia.edu intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1) 100 else: 101 # if the numa_bit is not specified, set the directory bits as the 102 # lowest bits above the block offset bits 103 intlv_size = options.cacheline_size 104 105 # Sets bits to be used for interleaving. Creates memory controllers 106 # attached to a directory controller. A separate controller is created 107 # for each address range as the abstract memory can handle only one 108 # contiguous address range as of now. 109 for dir_cntrl in dir_cntrls: 110 crossbar = None 111 if len(system.mem_ranges) > 1: 112 crossbar = IOXBar() 113 crossbars.append(crossbar) 114 dir_cntrl.memory = crossbar.slave 115 116 dir_ranges = [] 117 for r in system.mem_ranges: 118 mem_ctrl = MemConfig.create_mem_ctrl( 119 MemConfig.get(options.mem_type), r, index, options.num_dirs, 120 int(math.log(options.num_dirs, 2)), intlv_size) 121 122 if options.access_backing_store: 123 mem_ctrl.kvm_map=False 124 125 mem_ctrls.append(mem_ctrl) 126 dir_ranges.append(mem_ctrl.range) 127 128 if crossbar != None: 129 mem_ctrl.port = crossbar.master 130 else: 131 mem_ctrl.port = dir_cntrl.memory 132 133 # Enable low-power DRAM states if option is set 134 if issubclass(MemConfig.get(options.mem_type), DRAMCtrl): 135 mem_ctrl.enable_dram_powerdown = \ 136 options.enable_dram_powerdown 137 138 index += 1 139 dir_cntrl.addr_ranges = dir_ranges 140 141 system.mem_ctrls = mem_ctrls 142 143 if len(crossbars) > 0: 144 ruby.crossbars = crossbars 145 146 147def create_topology(controllers, options): 148 """ Called from create_system in configs/ruby/<protocol>.py 149 Must return an object which is a subclass of BaseTopology 150 found in configs/topologies/BaseTopology.py 151 This is a wrapper for the legacy topologies. 152 """ 153 exec("import topologies.%s as Topo" % options.topology) 154 topology = eval("Topo.%s(controllers)" % options.topology) 155 return topology 156 157def create_system(options, full_system, system, piobus = None, dma_ports = [], 158 bootmem=None): 159 160 system.ruby = RubySystem() 161 ruby = system.ruby 162 163 # Generate pseudo filesystem 164 FileSystemConfig.config_filesystem(system, options) 165 166 # Create the network object 167 (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 168 Network.create_network(options, ruby) 169 ruby.network = network 170 171 protocol = buildEnv['PROTOCOL'] 172 exec("from . import %s" % protocol) 173 try: 174 (cpu_sequencers, dir_cntrls, topology) = \ 175 eval("%s.create_system(options, full_system, system, dma_ports,\ 176 bootmem, ruby)" 177 % protocol) 178 except: 179 print("Error: could not create sytem for ruby protocol %s" % protocol) 180 raise 181 182 # Create the network topology 183 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 184 RouterClass) 185 186 # Register the topology elements with faux filesystem (SE mode only) 187 if not full_system: 188 topology.registerTopology(options) 189 190 191 # Initialize network based on topology 192 Network.init_network(options, network, InterfaceClass) 193 194 # Create a port proxy for connecting the system port. This is 195 # independent of the protocol and kept in the protocol-agnostic 196 # part (i.e. here). 197 sys_port_proxy = RubyPortProxy(ruby_system = ruby) 198 if piobus is not None: 199 sys_port_proxy.pio_master_port = piobus.slave 200 201 # Give the system port proxy a SimObject parent without creating a 202 # full-fledged controller 203 system.sys_port_proxy = sys_port_proxy 204 205 # Connect the system port for loading of binaries etc 206 system.system_port = system.sys_port_proxy.slave 207 208 setup_memory_controllers(system, ruby, dir_cntrls, options) 209 210 # Connect the cpu sequencers and the piobus 211 if piobus != None: 212 for cpu_seq in cpu_sequencers: 213 cpu_seq.pio_master_port = piobus.slave 214 cpu_seq.mem_master_port = piobus.slave 215 216 if buildEnv['TARGET_ISA'] == "x86": 217 cpu_seq.pio_slave_port = piobus.master 218 219 ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 220 ruby._cpu_ports = cpu_sequencers 221 ruby.num_of_sequencers = len(cpu_sequencers) 222 223 # Create a backing copy of physical memory in case required 224 if options.access_backing_store: 225 ruby.access_backing_store = True 226 ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 227 in_addr_map=False) 228 229def create_directories(options, bootmem, ruby_system, system): 230 dir_cntrl_nodes = [] 231 for i in range(options.num_dirs): 232 dir_cntrl = Directory_Controller() 233 dir_cntrl.version = i 234 dir_cntrl.directory = RubyDirectoryMemory() 235 dir_cntrl.ruby_system = ruby_system 236 237 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 238 dir_cntrl_nodes.append(dir_cntrl) 239 240 if bootmem is not None: 241 rom_dir_cntrl = Directory_Controller() 242 rom_dir_cntrl.directory = RubyDirectoryMemory() 243 rom_dir_cntrl.ruby_system = ruby_system 244 rom_dir_cntrl.version = i + 1 245 rom_dir_cntrl.memory = bootmem.port 246 rom_dir_cntrl.addr_ranges = bootmem.range 247 return (dir_cntrl_nodes, rom_dir_cntrl) 248 249 return (dir_cntrl_nodes, None) 250 251def send_evicts(options): 252 # currently, 2 scenarios warrant forwarding evictions to the CPU: 253 # 1. The O3 model must keep the LSQ coherent with the caches 254 # 2. The x86 mwait instruction is built on top of coherence invalidations 255 # 3. The local exclusive monitor in ARM systems 256 if options.cpu_type == "DerivO3CPU" or \ 257 buildEnv['TARGET_ISA'] in ('x86', 'arm'): 258 return True 259 return False 260