Ruby.py revision 12564:2778478ca882 
1# Copyright (c) 2012, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# Copyright (c) 2009 Advanced Micro Devices, Inc.
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Brad Beckmann
41
42from __future__ import print_function
43
44import math
45import m5
46from m5.objects import *
47from m5.defines import buildEnv
48from m5.util import addToPath, fatal
49
50from common import MemConfig
51
52from topologies import *
53from network import Network
54
55def define_options(parser):
56    # By default, ruby uses the simple timing cpu
57    parser.set_defaults(cpu_type="TimingSimpleCPU")
58
59    parser.add_option("--ruby-clock", action="store", type="string",
60                      default='2GHz',
61                      help="Clock for blocks running at Ruby system's speed")
62
63    parser.add_option("--access-backing-store", action="store_true", default=False,
64                      help="Should ruby maintain a second copy of memory")
65
66    # Options related to cache structure
67    parser.add_option("--ports", action="store", type="int", default=4,
68                      help="used of transitions per cycle which is a proxy \
69                            for the number of ports.")
70
71    # network options are in network/Network.py
72
73    # ruby mapping options
74    parser.add_option("--numa-high-bit", type="int", default=0,
75                      help="high order address bit to use for numa mapping. " \
76                           "0 = highest bit, not specified = lowest bit")
77
78    parser.add_option("--recycle-latency", type="int", default=10,
79                      help="Recycle latency for ruby controller input buffers")
80
81    protocol = buildEnv['PROTOCOL']
82    exec "import %s" % protocol
83    eval("%s.define_options(parser)" % protocol)
84    Network.define_options(parser)
85
86def setup_memory_controllers(system, ruby, dir_cntrls, options):
87    ruby.block_size_bytes = options.cacheline_size
88    ruby.memory_size_bits = 48
89
90    index = 0
91    mem_ctrls = []
92    crossbars = []
93
94    # Sets bits to be used for interleaving.  Creates memory controllers
95    # attached to a directory controller.  A separate controller is created
96    # for each address range as the abstract memory can handle only one
97    # contiguous address range as of now.
98    for dir_cntrl in dir_cntrls:
99        crossbar = None
100        if len(system.mem_ranges) > 1:
101            crossbar = IOXBar()
102            crossbars.append(crossbar)
103            dir_cntrl.memory = crossbar.slave
104
105        for r in system.mem_ranges:
106            mem_ctrl = MemConfig.create_mem_ctrl(
107                MemConfig.get(options.mem_type), r, index, options.num_dirs,
108                int(math.log(options.num_dirs, 2)), options.cacheline_size)
109
110            if options.access_backing_store:
111                mem_ctrl.kvm_map=False
112
113            mem_ctrls.append(mem_ctrl)
114
115            if crossbar != None:
116                mem_ctrl.port = crossbar.master
117            else:
118                mem_ctrl.port = dir_cntrl.memory
119
120        index += 1
121
122    system.mem_ctrls = mem_ctrls
123
124    if len(crossbars) > 0:
125        ruby.crossbars = crossbars
126
127
128def create_topology(controllers, options):
129    """ Called from create_system in configs/ruby/<protocol>.py
130        Must return an object which is a subclass of BaseTopology
131        found in configs/topologies/BaseTopology.py
132        This is a wrapper for the legacy topologies.
133    """
134    exec "import topologies.%s as Topo" % options.topology
135    topology = eval("Topo.%s(controllers)" % options.topology)
136    return topology
137
138def create_system(options, full_system, system, piobus = None, dma_ports = []):
139
140    system.ruby = RubySystem()
141    ruby = system.ruby
142
143    # Create the network object
144    (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
145        Network.create_network(options, ruby)
146    ruby.network = network
147
148    protocol = buildEnv['PROTOCOL']
149    exec "import %s" % protocol
150    try:
151        (cpu_sequencers, dir_cntrls, topology) = \
152             eval("%s.create_system(options, full_system, system, dma_ports,\
153                                    ruby)"
154                  % protocol)
155    except:
156        print("Error: could not create sytem for ruby protocol %s" % protocol)
157        raise
158
159    # Create the network topology
160    topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
161            RouterClass)
162
163    # Initialize network based on topology
164    Network.init_network(options, network, InterfaceClass)
165
166    # Create a port proxy for connecting the system port. This is
167    # independent of the protocol and kept in the protocol-agnostic
168    # part (i.e. here).
169    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
170    if piobus is not None:
171        sys_port_proxy.pio_master_port = piobus.slave
172
173    # Give the system port proxy a SimObject parent without creating a
174    # full-fledged controller
175    system.sys_port_proxy = sys_port_proxy
176
177    # Connect the system port for loading of binaries etc
178    system.system_port = system.sys_port_proxy.slave
179
180    setup_memory_controllers(system, ruby, dir_cntrls, options)
181
182    # Connect the cpu sequencers and the piobus
183    if piobus != None:
184        for cpu_seq in cpu_sequencers:
185            cpu_seq.pio_master_port = piobus.slave
186            cpu_seq.mem_master_port = piobus.slave
187
188            if buildEnv['TARGET_ISA'] == "x86":
189                cpu_seq.pio_slave_port = piobus.master
190
191    ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
192    ruby._cpu_ports = cpu_sequencers
193    ruby.num_of_sequencers = len(cpu_sequencers)
194
195    # Create a backing copy of physical memory in case required
196    if options.access_backing_store:
197        ruby.access_backing_store = True
198        ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
199                                     in_addr_map=False)
200
201def create_directories(options, mem_ranges, ruby_system):
202    dir_cntrl_nodes = []
203    if options.numa_high_bit:
204        numa_bit = options.numa_high_bit
205    else:
206        # if the numa_bit is not specified, set the directory bits as the
207        # lowest bits above the block offset bits, and the numa_bit as the
208        # highest of those directory bits
209        dir_bits = int(math.log(options.num_dirs, 2))
210        block_size_bits = int(math.log(options.cacheline_size, 2))
211        numa_bit = block_size_bits + dir_bits - 1
212
213    for i in xrange(options.num_dirs):
214        dir_ranges = []
215        for r in mem_ranges:
216            addr_range = m5.objects.AddrRange(r.start, size = r.size(),
217                                              intlvHighBit = numa_bit,
218                                              intlvBits = dir_bits,
219                                              intlvMatch = i)
220            dir_ranges.append(addr_range)
221
222        dir_cntrl = Directory_Controller()
223        dir_cntrl.version = i
224        dir_cntrl.directory = RubyDirectoryMemory()
225        dir_cntrl.ruby_system = ruby_system
226        dir_cntrl.addr_ranges = dir_ranges
227
228        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
229        dir_cntrl_nodes.append(dir_cntrl)
230    return dir_cntrl_nodes
231
232def send_evicts(options):
233    # currently, 2 scenarios warrant forwarding evictions to the CPU:
234    # 1. The O3 model must keep the LSQ coherent with the caches
235    # 2. The x86 mwait instruction is built on top of coherence invalidations
236    # 3. The local exclusive monitor in ARM systems
237    if options.cpu_type == "DerivO3CPU" or \
238       buildEnv['TARGET_ISA'] in ('x86', 'arm'):
239        return True
240    return False
241