Ruby.py revision 12066:a4fd03c9ca5a 
1# Copyright (c) 2012, 2017 ARM Limited
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# Copyright (c) 2009 Advanced Micro Devices, Inc.
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39#
40# Authors: Brad Beckmann
41
42import math
43import m5
44from m5.objects import *
45from m5.defines import buildEnv
46from m5.util import addToPath, fatal
47
48from common import MemConfig
49
50from topologies import *
51from network import Network
52
53def define_options(parser):
54    # By default, ruby uses the simple timing cpu
55    parser.set_defaults(cpu_type="TimingSimpleCPU")
56
57    parser.add_option("--ruby-clock", action="store", type="string",
58                      default='2GHz',
59                      help="Clock for blocks running at Ruby system's speed")
60
61    parser.add_option("--access-backing-store", action="store_true", default=False,
62                      help="Should ruby maintain a second copy of memory")
63
64    # Options related to cache structure
65    parser.add_option("--ports", action="store", type="int", default=4,
66                      help="used of transitions per cycle which is a proxy \
67                            for the number of ports.")
68
69    # network options are in network/Network.py
70
71    # ruby mapping options
72    parser.add_option("--numa-high-bit", type="int", default=0,
73                      help="high order address bit to use for numa mapping. " \
74                           "0 = highest bit, not specified = lowest bit")
75
76    parser.add_option("--recycle-latency", type="int", default=10,
77                      help="Recycle latency for ruby controller input buffers")
78
79    protocol = buildEnv['PROTOCOL']
80    exec "import %s" % protocol
81    eval("%s.define_options(parser)" % protocol)
82    Network.define_options(parser)
83
84def setup_memory_controllers(system, ruby, dir_cntrls, options):
85    ruby.block_size_bytes = options.cacheline_size
86    ruby.memory_size_bits = 48
87
88    index = 0
89    mem_ctrls = []
90    crossbars = []
91
92    # Sets bits to be used for interleaving.  Creates memory controllers
93    # attached to a directory controller.  A separate controller is created
94    # for each address range as the abstract memory can handle only one
95    # contiguous address range as of now.
96    for dir_cntrl in dir_cntrls:
97        crossbar = None
98        if len(system.mem_ranges) > 1:
99            crossbar = IOXBar()
100            crossbars.append(crossbar)
101            dir_cntrl.memory = crossbar.slave
102
103        for r in system.mem_ranges:
104            mem_ctrl = MemConfig.create_mem_ctrl(
105                MemConfig.get(options.mem_type), r, index, options.num_dirs,
106                int(math.log(options.num_dirs, 2)), options.cacheline_size)
107
108            if options.access_backing_store:
109                mem_ctrl.kvm_map=False
110
111            mem_ctrls.append(mem_ctrl)
112
113            if crossbar != None:
114                mem_ctrl.port = crossbar.master
115            else:
116                mem_ctrl.port = dir_cntrl.memory
117
118        index += 1
119
120    system.mem_ctrls = mem_ctrls
121
122    if len(crossbars) > 0:
123        ruby.crossbars = crossbars
124
125
126def create_topology(controllers, options):
127    """ Called from create_system in configs/ruby/<protocol>.py
128        Must return an object which is a subclass of BaseTopology
129        found in configs/topologies/BaseTopology.py
130        This is a wrapper for the legacy topologies.
131    """
132    exec "import topologies.%s as Topo" % options.topology
133    topology = eval("Topo.%s(controllers)" % options.topology)
134    return topology
135
136def create_system(options, full_system, system, piobus = None, dma_ports = []):
137
138    system.ruby = RubySystem()
139    ruby = system.ruby
140
141    # Create the network object
142    (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
143        Network.create_network(options, ruby)
144    ruby.network = network
145
146    protocol = buildEnv['PROTOCOL']
147    exec "import %s" % protocol
148    try:
149        (cpu_sequencers, dir_cntrls, topology) = \
150             eval("%s.create_system(options, full_system, system, dma_ports,\
151                                    ruby)"
152                  % protocol)
153    except:
154        print "Error: could not create sytem for ruby protocol %s" % protocol
155        raise
156
157    # Create the network topology
158    topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
159            RouterClass)
160
161    # Initialize network based on topology
162    Network.init_network(options, network, InterfaceClass)
163
164    # Create a port proxy for connecting the system port. This is
165    # independent of the protocol and kept in the protocol-agnostic
166    # part (i.e. here).
167    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
168    if piobus is not None:
169        sys_port_proxy.pio_master_port = piobus.slave
170
171    # Give the system port proxy a SimObject parent without creating a
172    # full-fledged controller
173    system.sys_port_proxy = sys_port_proxy
174
175    # Connect the system port for loading of binaries etc
176    system.system_port = system.sys_port_proxy.slave
177
178    setup_memory_controllers(system, ruby, dir_cntrls, options)
179
180    # Connect the cpu sequencers and the piobus
181    if piobus != None:
182        for cpu_seq in cpu_sequencers:
183            cpu_seq.pio_master_port = piobus.slave
184            cpu_seq.mem_master_port = piobus.slave
185
186            if buildEnv['TARGET_ISA'] == "x86":
187                cpu_seq.pio_slave_port = piobus.master
188
189    ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
190    ruby._cpu_ports = cpu_sequencers
191    ruby.num_of_sequencers = len(cpu_sequencers)
192
193    # Create a backing copy of physical memory in case required
194    if options.access_backing_store:
195        ruby.access_backing_store = True
196        ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
197                                     in_addr_map=False)
198
199def create_directories(options, mem_ranges, ruby_system):
200    dir_cntrl_nodes = []
201    if options.numa_high_bit:
202        numa_bit = options.numa_high_bit
203    else:
204        # if the numa_bit is not specified, set the directory bits as the
205        # lowest bits above the block offset bits, and the numa_bit as the
206        # highest of those directory bits
207        dir_bits = int(math.log(options.num_dirs, 2))
208        block_size_bits = int(math.log(options.cacheline_size, 2))
209        numa_bit = block_size_bits + dir_bits - 1
210
211    for i in xrange(options.num_dirs):
212        dir_ranges = []
213        for r in mem_ranges:
214            addr_range = m5.objects.AddrRange(r.start, size = r.size(),
215                                              intlvHighBit = numa_bit,
216                                              intlvBits = dir_bits,
217                                              intlvMatch = i)
218            dir_ranges.append(addr_range)
219
220        dir_cntrl = Directory_Controller()
221        dir_cntrl.version = i
222        dir_cntrl.directory = RubyDirectoryMemory()
223        dir_cntrl.ruby_system = ruby_system
224        dir_cntrl.addr_ranges = dir_ranges
225
226        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
227        dir_cntrl_nodes.append(dir_cntrl)
228    return dir_cntrl_nodes
229
230def send_evicts(options):
231    # currently, 2 scenarios warrant forwarding evictions to the CPU:
232    # 1. The O3 model must keep the LSQ coherent with the caches
233    # 2. The x86 mwait instruction is built on top of coherence invalidations
234    # 3. The local exclusive monitor in ARM systems
235    if options.cpu_type == "DerivO3CPU" or \
236       buildEnv['TARGET_ISA'] in ('x86', 'arm'):
237        return True
238    return False
239