Ruby.py revision 12014:f973caaf935d
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 153005Sstever@eecs.umich.edu# All rights reserved. 163005Sstever@eecs.umich.edu# 173005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 183005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 193005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 203005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 213005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 223005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 233005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 243005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 253005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 263005Sstever@eecs.umich.edu# this software without specific prior written permission. 273005Sstever@eecs.umich.edu# 283005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393005Sstever@eecs.umich.edu# 403005Sstever@eecs.umich.edu# Authors: Brad Beckmann 412710SN/A 422710SN/Aimport math 433005Sstever@eecs.umich.eduimport m5 442889SN/Afrom m5.objects import * 456654Snate@binkert.orgfrom m5.defines import buildEnv 466654Snate@binkert.orgfrom m5.util import addToPath, fatal 476654Snate@binkert.org 482667SN/Afrom common import MemConfig 496654Snate@binkert.org 506654Snate@binkert.orgfrom topologies import * 516654Snate@binkert.orgfrom network import Network 525457Ssaidi@eecs.umich.edu 536654Snate@binkert.orgdef define_options(parser): 548169SLisa.Hsu@amd.com # By default, ruby uses the simple timing cpu 559100SBrad.Beckmann@amd.com parser.set_defaults(cpu_type="TimingSimpleCPU") 568169SLisa.Hsu@amd.com 578920Snilay@cs.wisc.edu parser.add_option("--ruby-clock", action="store", type="string", 588169SLisa.Hsu@amd.com default='2GHz', 593395Shsul@eecs.umich.edu help="Clock for blocks running at Ruby system's speed") 606981SLisa.Hsu@amd.com 613448Shsul@eecs.umich.edu parser.add_option("--access-backing-store", action="store_true", default=False, 625369Ssaidi@eecs.umich.edu help="Should ruby maintain a second copy of memory") 633394Shsul@eecs.umich.edu 649197Snilay@cs.wisc.edu # Options related to cache structure 659197Snilay@cs.wisc.edu parser.add_option("--ports", action="store", type="int", default=4, 669197Snilay@cs.wisc.edu help="used of transitions per cycle which is a proxy \ 679197Snilay@cs.wisc.edu for the number of ports.") 689197Snilay@cs.wisc.edu 699197Snilay@cs.wisc.edu # network options are in network/Network.py 709197Snilay@cs.wisc.edu 719197Snilay@cs.wisc.edu # ruby mapping options 729197Snilay@cs.wisc.edu parser.add_option("--numa-high-bit", type="int", default=0, 739197Snilay@cs.wisc.edu help="high order address bit to use for numa mapping. " \ 749197Snilay@cs.wisc.edu "0 = highest bit, not specified = lowest bit") 759197Snilay@cs.wisc.edu 769197Snilay@cs.wisc.edu parser.add_option("--recycle-latency", type="int", default=10, 779197Snilay@cs.wisc.edu help="Recycle latency for ruby controller input buffers") 789197Snilay@cs.wisc.edu 799197Snilay@cs.wisc.edu protocol = buildEnv['PROTOCOL'] 809197Snilay@cs.wisc.edu exec "import %s" % protocol 819197Snilay@cs.wisc.edu eval("%s.define_options(parser)" % protocol) 829197Snilay@cs.wisc.edu Network.define_options(parser) 839197Snilay@cs.wisc.edu 849197Snilay@cs.wisc.edudef setup_memory_controllers(system, ruby, dir_cntrls, options): 859197Snilay@cs.wisc.edu ruby.block_size_bytes = options.cacheline_size 869197Snilay@cs.wisc.edu ruby.memory_size_bits = 48 879197Snilay@cs.wisc.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 889197Snilay@cs.wisc.edu 899217Snilay@cs.wisc.edu if options.numa_high_bit: 909197Snilay@cs.wisc.edu numa_bit = options.numa_high_bit 919197Snilay@cs.wisc.edu else: 929197Snilay@cs.wisc.edu # if the numa_bit is not specified, set the directory bits as the 939197Snilay@cs.wisc.edu # lowest bits above the block offset bits, and the numa_bit as the 949197Snilay@cs.wisc.edu # highest of those directory bits 959197Snilay@cs.wisc.edu dir_bits = int(math.log(options.num_dirs, 2)) 969197Snilay@cs.wisc.edu numa_bit = block_size_bits + dir_bits - 1 979197Snilay@cs.wisc.edu 989197Snilay@cs.wisc.edu index = 0 999197Snilay@cs.wisc.edu mem_ctrls = [] 1009197Snilay@cs.wisc.edu crossbars = [] 1019197Snilay@cs.wisc.edu 1029197Snilay@cs.wisc.edu # Sets bits to be used for interleaving. Creates memory controllers 1039197Snilay@cs.wisc.edu # attached to a directory controller. A separate controller is created 1049197Snilay@cs.wisc.edu # for each address range as the abstract memory can handle only one 1059197Snilay@cs.wisc.edu # contiguous address range as of now. 1069197Snilay@cs.wisc.edu for dir_cntrl in dir_cntrls: 1079197Snilay@cs.wisc.edu dir_cntrl.directory.numa_high_bit = numa_bit 1089197Snilay@cs.wisc.edu 1099197Snilay@cs.wisc.edu crossbar = None 1102957SN/A if len(system.mem_ranges) > 1: 1118920Snilay@cs.wisc.edu crossbar = IOXBar() 1128920Snilay@cs.wisc.edu crossbars.append(crossbar) 1132957SN/A dir_cntrl.memory = crossbar.slave 1148862Snilay@cs.wisc.edu 1158862Snilay@cs.wisc.edu for r in system.mem_ranges: 1168467Snilay@cs.wisc.edu mem_ctrl = MemConfig.create_mem_ctrl( 1172957SN/A MemConfig.get(options.mem_type), r, index, options.num_dirs, 1182957SN/A int(math.log(options.num_dirs, 2)), options.cacheline_size) 1192957SN/A 1202957SN/A if options.access_backing_store: 1212957SN/A mem_ctrl.kvm_map=False 1222957SN/A 1238167SLisa.Hsu@amd.com mem_ctrls.append(mem_ctrl) 1249197Snilay@cs.wisc.edu 1258167SLisa.Hsu@amd.com if crossbar != None: 1265369Ssaidi@eecs.umich.edu mem_ctrl.port = crossbar.master 1278167SLisa.Hsu@amd.com else: 1288167SLisa.Hsu@amd.com mem_ctrl.port = dir_cntrl.memory 1298167SLisa.Hsu@amd.com 1308167SLisa.Hsu@amd.com index += 1 1318167SLisa.Hsu@amd.com 1328167SLisa.Hsu@amd.com system.mem_ctrls = mem_ctrls 1338167SLisa.Hsu@amd.com 1348168SLisa.Hsu@amd.com if len(crossbars) > 0: 1358168SLisa.Hsu@amd.com ruby.crossbars = crossbars 1368168SLisa.Hsu@amd.com 1378168SLisa.Hsu@amd.com 1388167SLisa.Hsu@amd.comdef create_topology(controllers, options): 1398167SLisa.Hsu@amd.com """ Called from create_system in configs/ruby/<protocol>.py 1408168SLisa.Hsu@amd.com Must return an object which is a subclass of BaseTopology 1415369Ssaidi@eecs.umich.edu found in configs/topologies/BaseTopology.py 1428920Snilay@cs.wisc.edu This is a wrapper for the legacy topologies. 1439197Snilay@cs.wisc.edu """ 1448920Snilay@cs.wisc.edu exec "import topologies.%s as Topo" % options.topology 1458920Snilay@cs.wisc.edu topology = eval("Topo.%s(controllers)" % options.topology) 1468920Snilay@cs.wisc.edu return topology 1475369Ssaidi@eecs.umich.edu 1485369Ssaidi@eecs.umich.edudef create_system(options, full_system, system, piobus = None, dma_ports = []): 1498718Snilay@cs.wisc.edu 1509129Sandreas.hansson@arm.com system.ruby = RubySystem() 1519197Snilay@cs.wisc.edu ruby = system.ruby 1529197Snilay@cs.wisc.edu 1539197Snilay@cs.wisc.edu # Create the network object 1549197Snilay@cs.wisc.edu (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 1559197Snilay@cs.wisc.edu Network.create_network(options, ruby) 1563005Sstever@eecs.umich.edu ruby.network = network 1573395Shsul@eecs.umich.edu 1583395Shsul@eecs.umich.edu protocol = buildEnv['PROTOCOL'] 1598931Sandreas.hansson@arm.com exec "import %s" % protocol 1609036Sandreas.hansson@arm.com try: 1613395Shsul@eecs.umich.edu (cpu_sequencers, dir_cntrls, topology) = \ 1628926Sandreas.hansson@arm.com eval("%s.create_system(options, full_system, system, dma_ports,\ 1638926Sandreas.hansson@arm.com ruby)" 1648926Sandreas.hansson@arm.com % protocol) 1658926Sandreas.hansson@arm.com except: 1663395Shsul@eecs.umich.edu print "Error: could not create sytem for ruby protocol %s" % protocol 1679197Snilay@cs.wisc.edu raise 1689197Snilay@cs.wisc.edu 1699197Snilay@cs.wisc.edu # Create the network topology 1708957Sjayneel@cs.wisc.edu topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 1718957Sjayneel@cs.wisc.edu RouterClass) 1728957Sjayneel@cs.wisc.edu 1733005Sstever@eecs.umich.edu # Initialize network based on topology 1744968Sacolyte@umich.edu Network.init_network(options, network, InterfaceClass) 1759006Sandreas.hansson@arm.com 1764968Sacolyte@umich.edu # Create a port proxy for connecting the system port. This is 1778887Sgeoffrey.blake@arm.com # independent of the protocol and kept in the protocol-agnostic 1788887Sgeoffrey.blake@arm.com # part (i.e. here). 1798887Sgeoffrey.blake@arm.com sys_port_proxy = RubyPortProxy(ruby_system = ruby) 1808887Sgeoffrey.blake@arm.com if piobus is not None: 1818896Snilay@cs.wisc.edu sys_port_proxy.pio_master_port = piobus.slave 1828896Snilay@cs.wisc.edu 1838896Snilay@cs.wisc.edu # Give the system port proxy a SimObject parent without creating a 1848896Snilay@cs.wisc.edu # full-fledged controller 1858887Sgeoffrey.blake@arm.com system.sys_port_proxy = sys_port_proxy 1868887Sgeoffrey.blake@arm.com 1878887Sgeoffrey.blake@arm.com # Connect the system port for loading of binaries etc 1888896Snilay@cs.wisc.edu system.system_port = system.sys_port_proxy.slave 1898896Snilay@cs.wisc.edu 1908896Snilay@cs.wisc.edu setup_memory_controllers(system, ruby, dir_cntrls, options) 1918896Snilay@cs.wisc.edu 1928896Snilay@cs.wisc.edu # Connect the cpu sequencers and the piobus 1939268Smalek.musleh@gmail.com if piobus != None: 1949268Smalek.musleh@gmail.com for cpu_seq in cpu_sequencers: 1958896Snilay@cs.wisc.edu cpu_seq.pio_master_port = piobus.slave 1968896Snilay@cs.wisc.edu cpu_seq.mem_master_port = piobus.slave 1978896Snilay@cs.wisc.edu 1988896Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 1998896Snilay@cs.wisc.edu cpu_seq.pio_slave_port = piobus.master 2009222Shestness@cs.wisc.edu 2019268Smalek.musleh@gmail.com ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 2029268Smalek.musleh@gmail.com ruby._cpu_ports = cpu_sequencers 2039268Smalek.musleh@gmail.com ruby.num_of_sequencers = len(cpu_sequencers) 2049222Shestness@cs.wisc.edu 2059222Shestness@cs.wisc.edu # Create a backing copy of physical memory in case required 2068887Sgeoffrey.blake@arm.com if options.access_backing_store: 2078887Sgeoffrey.blake@arm.com ruby.access_backing_store = True 2088887Sgeoffrey.blake@arm.com ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 2098887Sgeoffrey.blake@arm.com in_addr_map=False) 2108887Sgeoffrey.blake@arm.com 2118801Sgblack@eecs.umich.edudef send_evicts(options): 2123481Shsul@eecs.umich.edu # currently, 2 scenarios warrant forwarding evictions to the CPU: 213 # 1. The O3 model must keep the LSQ coherent with the caches 214 # 2. The x86 mwait instruction is built on top of coherence invalidations 215 if options.cpu_type == "DerivO3CPU" or buildEnv['TARGET_ISA'] == 'x86': 216 return True 217 return False 218