Ruby.py revision 10551:d60a9bb99038
11689SN/A# Copyright (c) 2012 ARM Limited 22329SN/A# All rights reserved. 31689SN/A# 41689SN/A# The license below extends only to copyright in the software and shall 51689SN/A# not be construed as granting a license to any other intellectual 61689SN/A# property including but not limited to intellectual property relating 71689SN/A# to a hardware implementation of the functionality of the software 81689SN/A# licensed hereunder. You may use the software subject to the license 91689SN/A# terms below provided that you ensure that this notice is replicated 101689SN/A# unmodified and in its entirety in all distributions of the software, 111689SN/A# modified or unmodified, in source code or in binary form. 121689SN/A# 131689SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 141689SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 151689SN/A# All rights reserved. 161689SN/A# 171689SN/A# Redistribution and use in source and binary forms, with or without 181689SN/A# modification, are permitted provided that the following conditions are 191689SN/A# met: redistributions of source code must retain the above copyright 201689SN/A# notice, this list of conditions and the following disclaimer; 211689SN/A# redistributions in binary form must reproduce the above copyright 221689SN/A# notice, this list of conditions and the following disclaimer in the 231689SN/A# documentation and/or other materials provided with the distribution; 241689SN/A# neither the name of the copyright holders nor the names of its 251689SN/A# contributors may be used to endorse or promote products derived from 261689SN/A# this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292935Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321060SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331060SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343773Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353773Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361858SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371717SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385529Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391060SN/A# 406221Snate@binkert.org# Authors: Brad Beckmann 416221Snate@binkert.org 421061SN/Aimport math 435529Snate@binkert.orgimport m5 444329Sktlim@umich.edufrom m5.objects import * 454329Sktlim@umich.edufrom m5.defines import buildEnv 462292SN/Afrom m5.util import addToPath, fatal 472292SN/A 482292SN/Aimport MemConfig 492292SN/AaddToPath('../topologies') 503788Sgblack@eecs.umich.edu 513798Sgblack@eecs.umich.edudef define_options(parser): 525529Snate@binkert.org # By default, ruby uses the simple timing cpu 532361SN/A parser.set_defaults(cpu_type="timing") 541060SN/A 552292SN/A parser.add_option("--ruby-clock", action="store", type="string", 562292SN/A default='2GHz', 576221Snate@binkert.org help="Clock for blocks running at Ruby system's speed") 586221Snate@binkert.org 592292SN/A parser.add_option("--access-backing-store", action="store_true", default=False, 606221Snate@binkert.org help="Should ruby maintain a second copy of memory") 616221Snate@binkert.org 626221Snate@binkert.org # Options related to cache structure 632292SN/A parser.add_option("--ports", action="store", type="int", default=4, 646221Snate@binkert.org help="used of transitions per cycle which is a proxy \ 656221Snate@binkert.org for the number of ports.") 666221Snate@binkert.org 672292SN/A # ruby network options 686221Snate@binkert.org parser.add_option("--topology", type="string", default="Crossbar", 692292SN/A help="check src/mem/ruby/network/topologies for complete set") 706221Snate@binkert.org parser.add_option("--mesh-rows", type="int", default=1, 712292SN/A help="the number of rows in the mesh topology") 726221Snate@binkert.org parser.add_option("--garnet-network", type="choice", 732292SN/A choices=['fixed', 'flexible'], help="'fixed'|'flexible'") 742292SN/A parser.add_option("--network-fault-model", action="store_true", default=False, 752292SN/A help="enable network fault model: see src/mem/ruby/network/fault_model/") 762292SN/A 772292SN/A # ruby mapping options 782292SN/A parser.add_option("--numa-high-bit", type="int", default=0, 792292SN/A help="high order address bit to use for numa mapping. " \ 802292SN/A "0 = highest bit, not specified = lowest bit") 812292SN/A 822292SN/A parser.add_option("--recycle-latency", type="int", default=10, 832292SN/A help="Recycle latency for ruby controller input buffers") 841060SN/A 851060SN/A parser.add_option("--random_seed", type="int", default=1234, 861061SN/A help="Used for seeding the random number generator") 871060SN/A 882292SN/A protocol = buildEnv['PROTOCOL'] 891062SN/A exec "import %s" % protocol 901062SN/A eval("%s.define_options(parser)" % protocol) 912301SN/A 921062SN/Adef setup_memory_controllers(system, ruby, dir_cntrls, options): 931062SN/A ruby.block_size_bytes = options.cacheline_size 941062SN/A ruby.memory_size_bits = 48 952301SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 961062SN/A 971062SN/A if options.numa_high_bit: 981062SN/A numa_bit = options.numa_high_bit 992301SN/A else: 1001062SN/A # if the numa_bit is not specified, set the directory bits as the 1011062SN/A # lowest bits above the block offset bits, and the numa_bit as the 1022301SN/A # highest of those directory bits 1032301SN/A dir_bits = int(math.log(options.num_dirs, 2)) 1042301SN/A numa_bit = block_size_bits + dir_bits - 1 1052301SN/A 1062292SN/A index = 0 1072301SN/A mem_ctrls = [] 1082292SN/A crossbars = [] 1092292SN/A 1101062SN/A # Sets bits to be used for interleaving. Creates memory controllers 1112301SN/A # attached to a directory controller. A separate controller is created 1121062SN/A # for each address range as the abstract memory can handle only one 1131062SN/A # contiguous address range as of now. 1141062SN/A for dir_cntrl in dir_cntrls: 1152301SN/A dir_cntrl.directory.numa_high_bit = numa_bit 1161062SN/A 1171062SN/A crossbar = None 1181062SN/A if len(system.mem_ranges) > 1: 1192301SN/A crossbar = NoncoherentXBar() 1201062SN/A crossbars.append(crossbar) 1211062SN/A dir_cntrl.memory = crossbar.slave 1221062SN/A 1232301SN/A for r in system.mem_ranges: 1242292SN/A mem_ctrl = MemConfig.create_mem_ctrl( 1251062SN/A MemConfig.get(options.mem_type), r, index, options.num_dirs, 1261062SN/A int(math.log(options.num_dirs, 2)), options.cacheline_size) 1272301SN/A 1282292SN/A mem_ctrls.append(mem_ctrl) 1291062SN/A 1302292SN/A if crossbar != None: 1312301SN/A mem_ctrl.port = crossbar.master 1322292SN/A else: 1332292SN/A mem_ctrl.port = dir_cntrl.memory 1341062SN/A 1352301SN/A index += 1 1361062SN/A 1371062SN/A system.mem_ctrls = mem_ctrls 1381062SN/A 1392301SN/A if len(crossbars) > 0: 1401062SN/A ruby.crossbars = crossbars 1411062SN/A 1421062SN/A 1432301SN/Adef create_topology(controllers, options): 1441062SN/A """ Called from create_system in configs/ruby/<protocol>.py 1451062SN/A Must return an object which is a subclass of BaseTopology 1461062SN/A found in configs/topologies/BaseTopology.py 1472301SN/A This is a wrapper for the legacy topologies. 1481062SN/A """ 1491062SN/A exec "import %s as Topo" % options.topology 1501062SN/A topology = eval("Topo.%s(controllers)" % options.topology) 1512301SN/A return topology 1521062SN/A 1531062SN/Adef create_system(options, full_system, system, piobus = None, dma_ports = []): 1542301SN/A 1552301SN/A system.ruby = RubySystem() 1562301SN/A ruby = system.ruby 1572301SN/A 1582301SN/A # Set the network classes based on the command line options 1592301SN/A if options.garnet_network == "fixed": 1602301SN/A NetworkClass = GarnetNetwork_d 1612301SN/A IntLinkClass = GarnetIntLink_d 1622301SN/A ExtLinkClass = GarnetExtLink_d 1632301SN/A RouterClass = GarnetRouter_d 1642307SN/A InterfaceClass = GarnetNetworkInterface_d 1652307SN/A 1662307SN/A elif options.garnet_network == "flexible": 1672307SN/A NetworkClass = GarnetNetwork 1682307SN/A IntLinkClass = GarnetIntLink 1691062SN/A ExtLinkClass = GarnetExtLink 1701062SN/A RouterClass = GarnetRouter 1711062SN/A InterfaceClass = GarnetNetworkInterface 1721062SN/A 1732292SN/A else: 1741060SN/A NetworkClass = SimpleNetwork 1751060SN/A IntLinkClass = SimpleIntLink 1761060SN/A ExtLinkClass = SimpleExtLink 1771060SN/A RouterClass = Switch 1781060SN/A InterfaceClass = None 1791060SN/A 1801060SN/A # Instantiate the network object so that the controllers can connect to it. 1811060SN/A network = NetworkClass(ruby_system = ruby, topology = options.topology, 1821060SN/A routers = [], ext_links = [], int_links = [], netifs = []) 1831060SN/A ruby.network = network 1841060SN/A 1851060SN/A protocol = buildEnv['PROTOCOL'] 1861060SN/A exec "import %s" % protocol 1871061SN/A try: 1881060SN/A (cpu_sequencers, dir_cntrls, topology) = \ 1892292SN/A eval("%s.create_system(options, full_system, system, dma_ports,\ 1901060SN/A ruby)" 1911060SN/A % protocol) 1921060SN/A except: 1931060SN/A print "Error: could not create sytem for ruby protocol %s" % protocol 1941060SN/A raise 1951060SN/A 1961060SN/A # Create a port proxy for connecting the system port. This is 1971061SN/A # independent of the protocol and kept in the protocol-agnostic 1981060SN/A # part (i.e. here). 1992292SN/A sys_port_proxy = RubyPortProxy(ruby_system = ruby) 2001060SN/A 2011060SN/A # Give the system port proxy a SimObject parent without creating a 2021060SN/A # full-fledged controller 2031060SN/A system.sys_port_proxy = sys_port_proxy 2041060SN/A 2051060SN/A # Connect the system port for loading of binaries etc 2061060SN/A system.system_port = system.sys_port_proxy.slave 2071061SN/A 2081060SN/A # Create the network topology 2092292SN/A topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 2101060SN/A RouterClass) 2112329SN/A 2126221Snate@binkert.org if InterfaceClass != None: 2132292SN/A netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] 2142292SN/A network.netifs = netifs 2152292SN/A 2162292SN/A if options.network_fault_model: 2172292SN/A assert(options.garnet_network == "fixed") 2181060SN/A network.enable_fault_model = True 2191060SN/A network.fault_model = FaultModel() 2202292SN/A 2212292SN/A setup_memory_controllers(system, ruby, dir_cntrls, options) 2226221Snate@binkert.org 2232292SN/A # Connect the cpu sequencers and the piobus 2242292SN/A if piobus != None: 2252292SN/A for cpu_seq in cpu_sequencers: 2262292SN/A cpu_seq.pio_master_port = piobus.slave 2272292SN/A cpu_seq.mem_master_port = piobus.slave 2281061SN/A 2291060SN/A if buildEnv['TARGET_ISA'] == "x86": 2302292SN/A cpu_seq.pio_slave_port = piobus.master 2311060SN/A 2326221Snate@binkert.org ruby._cpu_ports = cpu_sequencers 2336221Snate@binkert.org ruby.num_of_sequencers = len(cpu_sequencers) 2341060SN/A ruby.random_seed = options.random_seed 2351060SN/A 2361061SN/Adef send_evicts(options): 2371060SN/A # currently, 2 scenarios warrant forwarding evictions to the CPU: 2382292SN/A # 1. The O3 model must keep the LSQ coherent with the caches 2391060SN/A # 2. The x86 mwait instruction is built on top of coherence invalidations 2402292SN/A if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 2412292SN/A return True 2421060SN/A return False 2432292SN/A 2442292SN/A # Create a backing copy of physical memory in case required 2452292SN/A if options.access_backing_store: 2462292SN/A ruby.phys_mem = SimpleMemory(range=AddrRange(options.mem_size), 2472292SN/A in_addr_map=False) 2481060SN/A