Ruby.py revision 13980
12068SN/A# Copyright (c) 2012, 2017-2018 ARM Limited 22068SN/A# All rights reserved. 32068SN/A# 42068SN/A# The license below extends only to copyright in the software and shall 52068SN/A# not be construed as granting a license to any other intellectual 62068SN/A# property including but not limited to intellectual property relating 72068SN/A# to a hardware implementation of the functionality of the software 82068SN/A# licensed hereunder. You may use the software subject to the license 92068SN/A# terms below provided that you ensure that this notice is replicated 102068SN/A# unmodified and in its entirety in all distributions of the software, 112068SN/A# modified or unmodified, in source code or in binary form. 122068SN/A# 132068SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 142068SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 152068SN/A# All rights reserved. 162068SN/A# 172068SN/A# Redistribution and use in source and binary forms, with or without 182068SN/A# modification, are permitted provided that the following conditions are 192068SN/A# met: redistributions of source code must retain the above copyright 202068SN/A# notice, this list of conditions and the following disclaimer; 212068SN/A# redistributions in binary form must reproduce the above copyright 222068SN/A# notice, this list of conditions and the following disclaimer in the 232068SN/A# documentation and/or other materials provided with the distribution; 242068SN/A# neither the name of the copyright holders nor the names of its 252068SN/A# contributors may be used to endorse or promote products derived from 262068SN/A# this software without specific prior written permission. 272068SN/A# 282665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312068SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322649Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332649Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342649Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352649Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362649Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372068SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382068SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392068SN/A# 402068SN/A# Authors: Brad Beckmann 412068SN/A 422068SN/Afrom __future__ import print_function 432068SN/A 442068SN/Aimport math 452068SN/Aimport m5 465736Snate@binkert.orgfrom m5.objects import * 472068SN/Afrom m5.defines import buildEnv 482068SN/Afrom m5.util import addToPath, fatal 496181Sksewell@umich.edu 506181Sksewell@umich.eduaddToPath('../') 512068SN/A 522068SN/Afrom common import MemConfig 532068SN/Afrom common import FileSystemConfig 542068SN/A 552068SN/Afrom topologies import * 562068SN/Afrom network import Network 572068SN/A 582068SN/Adef define_options(parser): 592068SN/A # By default, ruby uses the simple timing cpu 602068SN/A parser.set_defaults(cpu_type="TimingSimpleCPU") 612068SN/A 622068SN/A parser.add_option("--ruby-clock", action="store", type="string", 632068SN/A default='2GHz', 642068SN/A help="Clock for blocks running at Ruby system's speed") 652068SN/A 662068SN/A parser.add_option("--access-backing-store", action="store_true", default=False, 672068SN/A help="Should ruby maintain a second copy of memory") 682068SN/A 696181Sksewell@umich.edu # Options related to cache structure 706181Sksewell@umich.edu parser.add_option("--ports", action="store", type="int", default=4, 712068SN/A help="used of transitions per cycle which is a proxy \ 722068SN/A for the number of ports.") 732068SN/A 742068SN/A # network options are in network/Network.py 752068SN/A 762068SN/A # ruby mapping options 772068SN/A parser.add_option("--numa-high-bit", type="int", default=0, 782068SN/A help="high order address bit to use for numa mapping. " \ 792068SN/A "0 = highest bit, not specified = lowest bit") 802068SN/A 812068SN/A parser.add_option("--recycle-latency", type="int", default=10, 822068SN/A help="Recycle latency for ruby controller input buffers") 832068SN/A 842068SN/A protocol = buildEnv['PROTOCOL'] 852068SN/A exec("from . import %s" % protocol) 866181Sksewell@umich.edu eval("%s.define_options(parser)" % protocol) 876181Sksewell@umich.edu Network.define_options(parser) 882068SN/A 892068SN/Adef setup_memory_controllers(system, ruby, dir_cntrls, options): 902068SN/A ruby.block_size_bytes = options.cacheline_size 912068SN/A ruby.memory_size_bits = 48 922068SN/A 932068SN/A index = 0 942068SN/A mem_ctrls = [] 952068SN/A crossbars = [] 962068SN/A 972068SN/A if options.numa_high_bit: 982068SN/A dir_bits = int(math.log(options.num_dirs, 2)) 992068SN/A intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1) 1002068SN/A else: 1012068SN/A # if the numa_bit is not specified, set the directory bits as the 1022068SN/A # lowest bits above the block offset bits 1032068SN/A intlv_size = options.cacheline_size 1042068SN/A 1052068SN/A # Sets bits to be used for interleaving. Creates memory controllers 1062068SN/A # attached to a directory controller. A separate controller is created 1072068SN/A # for each address range as the abstract memory can handle only one 1082068SN/A # contiguous address range as of now. 1092068SN/A for dir_cntrl in dir_cntrls: 1102068SN/A crossbar = None 1112068SN/A if len(system.mem_ranges) > 1: 1122068SN/A crossbar = IOXBar() 1133953Sstever@eecs.umich.edu crossbars.append(crossbar) 1142068SN/A dir_cntrl.memory = crossbar.slave 1152068SN/A 1162068SN/A dir_ranges = [] 1172068SN/A for r in system.mem_ranges: 1182068SN/A mem_ctrl = MemConfig.create_mem_ctrl( 1192068SN/A MemConfig.get(options.mem_type), r, index, options.num_dirs, 1202068SN/A int(math.log(options.num_dirs, 2)), intlv_size) 1212068SN/A 1222068SN/A if options.access_backing_store: 1232068SN/A mem_ctrl.kvm_map=False 1242068SN/A 1252068SN/A mem_ctrls.append(mem_ctrl) 1262068SN/A dir_ranges.append(mem_ctrl.range) 1272068SN/A 1282068SN/A if crossbar != None: 1292068SN/A mem_ctrl.port = crossbar.master 1302227SN/A else: 1312068SN/A mem_ctrl.port = dir_cntrl.memory 1322068SN/A 1332095SN/A index += 1 1346181Sksewell@umich.edu dir_cntrl.addr_ranges = dir_ranges 1356181Sksewell@umich.edu 1362095SN/A system.mem_ctrls = mem_ctrls 1372095SN/A 1382095SN/A if len(crossbars) > 0: 1392068SN/A ruby.crossbars = crossbars 1402068SN/A 1412068SN/A 1422095SN/Adef create_topology(controllers, options): 1436181Sksewell@umich.edu """ Called from create_system in configs/ruby/<protocol>.py 1446181Sksewell@umich.edu Must return an object which is a subclass of BaseTopology 1456181Sksewell@umich.edu found in configs/topologies/BaseTopology.py 1466181Sksewell@umich.edu This is a wrapper for the legacy topologies. 1472095SN/A """ 1482132SN/A exec("import topologies.%s as Topo" % options.topology) 1492095SN/A topology = eval("Topo.%s(controllers)" % options.topology) 1502095SN/A return topology 1512095SN/A 1522095SN/Adef create_system(options, full_system, system, piobus = None, dma_ports = [], 1533349Sbinkertn@umich.edu bootmem=None): 1542623SN/A 1552095SN/A system.ruby = RubySystem() 1562095SN/A ruby = system.ruby 1576181Sksewell@umich.edu 1586181Sksewell@umich.edu # Generate pseudo filesystem 1596181Sksewell@umich.edu FileSystemConfig.config_filesystem(system, options) 1602068SN/A 1613953Sstever@eecs.umich.edu # Create the network object 1622068SN/A (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 1633953Sstever@eecs.umich.edu Network.create_network(options, ruby) 1642068SN/A ruby.network = network 1652068SN/A 1666181Sksewell@umich.edu protocol = buildEnv['PROTOCOL'] 1676181Sksewell@umich.edu exec("from . import %s" % protocol) 1682068SN/A try: 1692068SN/A (cpu_sequencers, dir_cntrls, topology) = \ 1702132SN/A eval("%s.create_system(options, full_system, system, dma_ports,\ 1712068SN/A bootmem, ruby)" 1722068SN/A % protocol) 1732068SN/A except: 1742068SN/A print("Error: could not create sytem for ruby protocol %s" % protocol) 1753953Sstever@eecs.umich.edu raise 1762068SN/A 1772090SN/A # Create the network topology 1782068SN/A topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 1792068SN/A RouterClass) 1802068SN/A 1812068SN/A # Register the topology elements with faux filesystem (SE mode only) 1822068SN/A if not full_system: 1832068SN/A topology.registerTopology(options) 1842068SN/A 1852068SN/A 1862068SN/A # Initialize network based on topology 1872069SN/A Network.init_network(options, network, InterfaceClass) 1882132SN/A 1892068SN/A # Create a port proxy for connecting the system port. This is 1902068SN/A # independent of the protocol and kept in the protocol-agnostic 1912068SN/A # part (i.e. here). 1922132SN/A sys_port_proxy = RubyPortProxy(ruby_system = ruby) 1932068SN/A if piobus is not None: 1942068SN/A sys_port_proxy.pio_master_port = piobus.slave 1952068SN/A 1962069SN/A # Give the system port proxy a SimObject parent without creating a 1972068SN/A # full-fledged controller 1982068SN/A system.sys_port_proxy = sys_port_proxy 1992090SN/A 2008442Sgblack@eecs.umich.edu # Connect the system port for loading of binaries etc 2012068SN/A system.system_port = system.sys_port_proxy.slave 2022068SN/A 2032068SN/A setup_memory_controllers(system, ruby, dir_cntrls, options) 2042090SN/A 2052069SN/A # Connect the cpu sequencers and the piobus 2062069SN/A if piobus != None: 2072069SN/A for cpu_seq in cpu_sequencers: 2082069SN/A cpu_seq.pio_master_port = piobus.slave 2092069SN/A cpu_seq.mem_master_port = piobus.slave 2102069SN/A 2112069SN/A if buildEnv['TARGET_ISA'] == "x86": 2122069SN/A cpu_seq.pio_slave_port = piobus.master 2132095SN/A 2142132SN/A ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 2152095SN/A ruby._cpu_ports = cpu_sequencers 2162095SN/A ruby.num_of_sequencers = len(cpu_sequencers) 2172095SN/A 2182132SN/A # Create a backing copy of physical memory in case required 2192095SN/A if options.access_backing_store: 2202095SN/A ruby.access_backing_store = True 2212095SN/A ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 2222095SN/A in_addr_map=False) 2232095SN/A 2242095SN/Adef create_directories(options, bootmem, ruby_system, system): 2252098SN/A dir_cntrl_nodes = [] 2268442Sgblack@eecs.umich.edu for i in range(options.num_dirs): 2272095SN/A dir_cntrl = Directory_Controller() 2282095SN/A dir_cntrl.version = i 2292095SN/A dir_cntrl.directory = RubyDirectoryMemory() 2302095SN/A dir_cntrl.ruby_system = ruby_system 2312095SN/A 2322095SN/A exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 2332095SN/A dir_cntrl_nodes.append(dir_cntrl) 2342095SN/A 2353349Sbinkertn@umich.edu if bootmem is not None: 2362095SN/A rom_dir_cntrl = Directory_Controller() 2372095SN/A rom_dir_cntrl.directory = RubyDirectoryMemory() 2382095SN/A rom_dir_cntrl.ruby_system = ruby_system 2392132SN/A rom_dir_cntrl.version = i + 1 2402095SN/A rom_dir_cntrl.memory = bootmem.port 2412095SN/A rom_dir_cntrl.addr_ranges = bootmem.range 2422506SN/A return (dir_cntrl_nodes, rom_dir_cntrl) 2432095SN/A 2448442Sgblack@eecs.umich.edu return (dir_cntrl_nodes, None) 2452095SN/A 2462098SN/Adef send_evicts(options): 2472095SN/A # currently, 2 scenarios warrant forwarding evictions to the CPU: 2482095SN/A # 1. The O3 model must keep the LSQ coherent with the caches 2492095SN/A # 2. The x86 mwait instruction is built on top of coherence invalidations 2502098SN/A # 3. The local exclusive monitor in ARM systems 2512095SN/A if options.cpu_type == "DerivO3CPU" or \ 2522095SN/A buildEnv['TARGET_ISA'] in ('x86', 'arm'): 2532095SN/A return True 2542095SN/A return False 2552095SN/A