Ruby.py revision 13400
112598Snikos.nikoleris@arm.com# Copyright (c) 2012, 2017-2018 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 136892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 146892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 156892SBrad.Beckmann@amd.com# All rights reserved. 166892SBrad.Beckmann@amd.com# 176892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 186892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 196892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 206892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 216892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 226892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 236892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 246892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 256892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 266892SBrad.Beckmann@amd.com# this software without specific prior written permission. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396892SBrad.Beckmann@amd.com# 406892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 416892SBrad.Beckmann@amd.com 4212564Sgabeblack@google.comfrom __future__ import print_function 4312564Sgabeblack@google.com 447563SBrad.Beckmann@amd.comimport math 456892SBrad.Beckmann@amd.comimport m5 466892SBrad.Beckmann@amd.comfrom m5.objects import * 476892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 4810118Snilay@cs.wisc.edufrom m5.util import addToPath, fatal 4910118Snilay@cs.wisc.edu 5013400Sodanrc@yahoo.com.braddToPath('../') 5113400Sodanrc@yahoo.com.br 5211682Sandreas.hansson@arm.comfrom common import MemConfig 5311662Stushar@ece.gatech.edu 5411670Sandreas.hansson@arm.comfrom topologies import * 5511670Sandreas.hansson@arm.comfrom network import Network 566892SBrad.Beckmann@amd.com 577538SBrad.Beckmann@amd.comdef define_options(parser): 588939SBrad.Beckmann@amd.com # By default, ruby uses the simple timing cpu 5912014Sgabeblack@google.com parser.set_defaults(cpu_type="TimingSimpleCPU") 608939SBrad.Beckmann@amd.com 619791Sakash.bagdia@arm.com parser.add_option("--ruby-clock", action="store", type="string", 629791Sakash.bagdia@arm.com default='2GHz', 639791Sakash.bagdia@arm.com help="Clock for blocks running at Ruby system's speed") 649791Sakash.bagdia@arm.com 6510525Snilay@cs.wisc.edu parser.add_option("--access-backing-store", action="store_true", default=False, 6610525Snilay@cs.wisc.edu help="Should ruby maintain a second copy of memory") 6710525Snilay@cs.wisc.edu 689841Snilay@cs.wisc.edu # Options related to cache structure 699841Snilay@cs.wisc.edu parser.add_option("--ports", action="store", type="int", default=4, 709841Snilay@cs.wisc.edu help="used of transitions per cycle which is a proxy \ 719841Snilay@cs.wisc.edu for the number of ports.") 729841Snilay@cs.wisc.edu 7311662Stushar@ece.gatech.edu # network options are in network/Network.py 747538SBrad.Beckmann@amd.com 757538SBrad.Beckmann@amd.com # ruby mapping options 767917SBrad.Beckmann@amd.com parser.add_option("--numa-high-bit", type="int", default=0, 777563SBrad.Beckmann@amd.com help="high order address bit to use for numa mapping. " \ 787563SBrad.Beckmann@amd.com "0 = highest bit, not specified = lowest bit") 797538SBrad.Beckmann@amd.com 807566SBrad.Beckmann@amd.com parser.add_option("--recycle-latency", type="int", default=10, 817566SBrad.Beckmann@amd.com help="Recycle latency for ruby controller input buffers") 827809Snilay@cs.wisc.edu 837538SBrad.Beckmann@amd.com protocol = buildEnv['PROTOCOL'] 847538SBrad.Beckmann@amd.com exec "import %s" % protocol 857538SBrad.Beckmann@amd.com eval("%s.define_options(parser)" % protocol) 8611670Sandreas.hansson@arm.com Network.define_options(parser) 877538SBrad.Beckmann@amd.com 8810524Snilay@cs.wisc.edudef setup_memory_controllers(system, ruby, dir_cntrls, options): 8910524Snilay@cs.wisc.edu ruby.block_size_bytes = options.cacheline_size 9010524Snilay@cs.wisc.edu ruby.memory_size_bits = 48 9110524Snilay@cs.wisc.edu 9210524Snilay@cs.wisc.edu index = 0 9310524Snilay@cs.wisc.edu mem_ctrls = [] 9410524Snilay@cs.wisc.edu crossbars = [] 9510524Snilay@cs.wisc.edu 9612976Snikos.nikoleris@arm.com if options.numa_high_bit: 9712976Snikos.nikoleris@arm.com dir_bits = int(math.log(options.num_dirs, 2)) 9812976Snikos.nikoleris@arm.com intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1) 9912976Snikos.nikoleris@arm.com else: 10012976Snikos.nikoleris@arm.com # if the numa_bit is not specified, set the directory bits as the 10112976Snikos.nikoleris@arm.com # lowest bits above the block offset bits 10212976Snikos.nikoleris@arm.com intlv_size = options.cacheline_size 10312976Snikos.nikoleris@arm.com 10410524Snilay@cs.wisc.edu # Sets bits to be used for interleaving. Creates memory controllers 10510524Snilay@cs.wisc.edu # attached to a directory controller. A separate controller is created 10610524Snilay@cs.wisc.edu # for each address range as the abstract memory can handle only one 10710524Snilay@cs.wisc.edu # contiguous address range as of now. 10810524Snilay@cs.wisc.edu for dir_cntrl in dir_cntrls: 10910524Snilay@cs.wisc.edu crossbar = None 11010524Snilay@cs.wisc.edu if len(system.mem_ranges) > 1: 11110720Sandreas.hansson@arm.com crossbar = IOXBar() 11210524Snilay@cs.wisc.edu crossbars.append(crossbar) 11310524Snilay@cs.wisc.edu dir_cntrl.memory = crossbar.slave 11410524Snilay@cs.wisc.edu 11512976Snikos.nikoleris@arm.com dir_ranges = [] 11610524Snilay@cs.wisc.edu for r in system.mem_ranges: 11710524Snilay@cs.wisc.edu mem_ctrl = MemConfig.create_mem_ctrl( 11810524Snilay@cs.wisc.edu MemConfig.get(options.mem_type), r, index, options.num_dirs, 11912976Snikos.nikoleris@arm.com int(math.log(options.num_dirs, 2)), intlv_size) 12010524Snilay@cs.wisc.edu 12111616Sdavid.j.hashe@gmail.com if options.access_backing_store: 12211616Sdavid.j.hashe@gmail.com mem_ctrl.kvm_map=False 12311616Sdavid.j.hashe@gmail.com 12410524Snilay@cs.wisc.edu mem_ctrls.append(mem_ctrl) 12512976Snikos.nikoleris@arm.com dir_ranges.append(mem_ctrl.range) 12610524Snilay@cs.wisc.edu 12710524Snilay@cs.wisc.edu if crossbar != None: 12810524Snilay@cs.wisc.edu mem_ctrl.port = crossbar.master 12910524Snilay@cs.wisc.edu else: 13010524Snilay@cs.wisc.edu mem_ctrl.port = dir_cntrl.memory 13110524Snilay@cs.wisc.edu 13210524Snilay@cs.wisc.edu index += 1 13312976Snikos.nikoleris@arm.com dir_cntrl.addr_ranges = dir_ranges 13410524Snilay@cs.wisc.edu 13510524Snilay@cs.wisc.edu system.mem_ctrls = mem_ctrls 13610524Snilay@cs.wisc.edu 13710524Snilay@cs.wisc.edu if len(crossbars) > 0: 13810524Snilay@cs.wisc.edu ruby.crossbars = crossbars 13910524Snilay@cs.wisc.edu 14010524Snilay@cs.wisc.edu 1419100SBrad.Beckmann@amd.comdef create_topology(controllers, options): 1429100SBrad.Beckmann@amd.com """ Called from create_system in configs/ruby/<protocol>.py 1439100SBrad.Beckmann@amd.com Must return an object which is a subclass of BaseTopology 1449100SBrad.Beckmann@amd.com found in configs/topologies/BaseTopology.py 1459100SBrad.Beckmann@amd.com This is a wrapper for the legacy topologies. 1469100SBrad.Beckmann@amd.com """ 14711670Sandreas.hansson@arm.com exec "import topologies.%s as Topo" % options.topology 1489100SBrad.Beckmann@amd.com topology = eval("Topo.%s(controllers)" % options.topology) 1499100SBrad.Beckmann@amd.com return topology 1509100SBrad.Beckmann@amd.com 15112598Snikos.nikoleris@arm.comdef create_system(options, full_system, system, piobus = None, dma_ports = [], 15212598Snikos.nikoleris@arm.com bootmem=None): 1536892SBrad.Beckmann@amd.com 15410524Snilay@cs.wisc.edu system.ruby = RubySystem() 1558436SBrad.Beckmann@amd.com ruby = system.ruby 1568436SBrad.Beckmann@amd.com 15711662Stushar@ece.gatech.edu # Create the network object 15811662Stushar@ece.gatech.edu (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 15911662Stushar@ece.gatech.edu Network.create_network(options, ruby) 16010311Snilay@cs.wisc.edu ruby.network = network 16110311Snilay@cs.wisc.edu 16210551Ssteve.reinhardt@amd.com protocol = buildEnv['PROTOCOL'] 16310551Ssteve.reinhardt@amd.com exec "import %s" % protocol 16410311Snilay@cs.wisc.edu try: 16510311Snilay@cs.wisc.edu (cpu_sequencers, dir_cntrls, topology) = \ 16610551Ssteve.reinhardt@amd.com eval("%s.create_system(options, full_system, system, dma_ports,\ 16712598Snikos.nikoleris@arm.com bootmem, ruby)" 16810551Ssteve.reinhardt@amd.com % protocol) 16910311Snilay@cs.wisc.edu except: 17012564Sgabeblack@google.com print("Error: could not create sytem for ruby protocol %s" % protocol) 17110311Snilay@cs.wisc.edu raise 17210311Snilay@cs.wisc.edu 17311662Stushar@ece.gatech.edu # Create the network topology 17411662Stushar@ece.gatech.edu topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 17511662Stushar@ece.gatech.edu RouterClass) 17611662Stushar@ece.gatech.edu 17711662Stushar@ece.gatech.edu # Initialize network based on topology 17811662Stushar@ece.gatech.edu Network.init_network(options, network, InterfaceClass) 17911662Stushar@ece.gatech.edu 18010311Snilay@cs.wisc.edu # Create a port proxy for connecting the system port. This is 18110311Snilay@cs.wisc.edu # independent of the protocol and kept in the protocol-agnostic 18210311Snilay@cs.wisc.edu # part (i.e. here). 18310311Snilay@cs.wisc.edu sys_port_proxy = RubyPortProxy(ruby_system = ruby) 18411596Sandreas.sandberg@arm.com if piobus is not None: 18511596Sandreas.sandberg@arm.com sys_port_proxy.pio_master_port = piobus.slave 18610311Snilay@cs.wisc.edu 18710311Snilay@cs.wisc.edu # Give the system port proxy a SimObject parent without creating a 18810311Snilay@cs.wisc.edu # full-fledged controller 18910311Snilay@cs.wisc.edu system.sys_port_proxy = sys_port_proxy 19010311Snilay@cs.wisc.edu 19110311Snilay@cs.wisc.edu # Connect the system port for loading of binaries etc 19210311Snilay@cs.wisc.edu system.system_port = system.sys_port_proxy.slave 1939148Spowerjg@cs.wisc.edu 19410524Snilay@cs.wisc.edu setup_memory_controllers(system, ruby, dir_cntrls, options) 19510116Snilay@cs.wisc.edu 19610116Snilay@cs.wisc.edu # Connect the cpu sequencers and the piobus 19710116Snilay@cs.wisc.edu if piobus != None: 19810116Snilay@cs.wisc.edu for cpu_seq in cpu_sequencers: 19910116Snilay@cs.wisc.edu cpu_seq.pio_master_port = piobus.slave 20010116Snilay@cs.wisc.edu cpu_seq.mem_master_port = piobus.slave 20110116Snilay@cs.wisc.edu 20210116Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 20310116Snilay@cs.wisc.edu cpu_seq.pio_slave_port = piobus.master 20410116Snilay@cs.wisc.edu 20511172Snilay@cs.wisc.edu ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 20610120Snilay@cs.wisc.edu ruby._cpu_ports = cpu_sequencers 20710012Snilay@cs.wisc.edu ruby.num_of_sequencers = len(cpu_sequencers) 20810525Snilay@cs.wisc.edu 20910630Snilay@cs.wisc.edu # Create a backing copy of physical memory in case required 21010630Snilay@cs.wisc.edu if options.access_backing_store: 21110706Spower.jg@gmail.com ruby.access_backing_store = True 21210706Spower.jg@gmail.com ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 21310630Snilay@cs.wisc.edu in_addr_map=False) 21410630Snilay@cs.wisc.edu 21512976Snikos.nikoleris@arm.comdef create_directories(options, bootmem, ruby_system, system): 21612065Snikos.nikoleris@arm.com dir_cntrl_nodes = [] 21712065Snikos.nikoleris@arm.com for i in xrange(options.num_dirs): 21812065Snikos.nikoleris@arm.com dir_cntrl = Directory_Controller() 21912065Snikos.nikoleris@arm.com dir_cntrl.version = i 22012065Snikos.nikoleris@arm.com dir_cntrl.directory = RubyDirectoryMemory() 22112065Snikos.nikoleris@arm.com dir_cntrl.ruby_system = ruby_system 22212065Snikos.nikoleris@arm.com 22312065Snikos.nikoleris@arm.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 22412065Snikos.nikoleris@arm.com dir_cntrl_nodes.append(dir_cntrl) 22512598Snikos.nikoleris@arm.com 22612598Snikos.nikoleris@arm.com if bootmem is not None: 22712598Snikos.nikoleris@arm.com rom_dir_cntrl = Directory_Controller() 22812598Snikos.nikoleris@arm.com rom_dir_cntrl.directory = RubyDirectoryMemory() 22912598Snikos.nikoleris@arm.com rom_dir_cntrl.ruby_system = ruby_system 23012598Snikos.nikoleris@arm.com rom_dir_cntrl.version = i + 1 23112598Snikos.nikoleris@arm.com rom_dir_cntrl.memory = bootmem.port 23212598Snikos.nikoleris@arm.com rom_dir_cntrl.addr_ranges = bootmem.range 23312598Snikos.nikoleris@arm.com return (dir_cntrl_nodes, rom_dir_cntrl) 23412598Snikos.nikoleris@arm.com 23512598Snikos.nikoleris@arm.com return (dir_cntrl_nodes, None) 23612065Snikos.nikoleris@arm.com 23710529Smorr@cs.wisc.edudef send_evicts(options): 23810529Smorr@cs.wisc.edu # currently, 2 scenarios warrant forwarding evictions to the CPU: 23910529Smorr@cs.wisc.edu # 1. The O3 model must keep the LSQ coherent with the caches 24010529Smorr@cs.wisc.edu # 2. The x86 mwait instruction is built on top of coherence invalidations 24112066Snikos.nikoleris@arm.com # 3. The local exclusive monitor in ARM systems 24212066Snikos.nikoleris@arm.com if options.cpu_type == "DerivO3CPU" or \ 24312066Snikos.nikoleris@arm.com buildEnv['TARGET_ISA'] in ('x86', 'arm'): 24410529Smorr@cs.wisc.edu return True 24510529Smorr@cs.wisc.edu return False 246