Ruby.py revision 12564
111988Sandreas.sandberg@arm.com# Copyright (c) 2012, 2017 ARM Limited 211988Sandreas.sandberg@arm.com# All rights reserved. 311988Sandreas.sandberg@arm.com# 411988Sandreas.sandberg@arm.com# The license below extends only to copyright in the software and shall 511988Sandreas.sandberg@arm.com# not be construed as granting a license to any other intellectual 611988Sandreas.sandberg@arm.com# property including but not limited to intellectual property relating 711988Sandreas.sandberg@arm.com# to a hardware implementation of the functionality of the software 811988Sandreas.sandberg@arm.com# licensed hereunder. You may use the software subject to the license 911988Sandreas.sandberg@arm.com# terms below provided that you ensure that this notice is replicated 1011988Sandreas.sandberg@arm.com# unmodified and in its entirety in all distributions of the software, 1111988Sandreas.sandberg@arm.com# modified or unmodified, in source code or in binary form. 1211988Sandreas.sandberg@arm.com# 1311988Sandreas.sandberg@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 1411988Sandreas.sandberg@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 1511988Sandreas.sandberg@arm.com# All rights reserved. 1611988Sandreas.sandberg@arm.com# 1711988Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without 1811988Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are 1911988Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright 2011988Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer; 2111988Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright 2211988Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the 2311988Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution; 2411988Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its 2511988Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from 2611988Sandreas.sandberg@arm.com# this software without specific prior written permission. 2711988Sandreas.sandberg@arm.com# 2811988Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911988Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011988Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111988Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211988Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311988Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411988Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511988Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611988Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711988Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811988Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911988Sandreas.sandberg@arm.com# 4011988Sandreas.sandberg@arm.com# Authors: Brad Beckmann 4111988Sandreas.sandberg@arm.com 4211988Sandreas.sandberg@arm.comfrom __future__ import print_function 4311988Sandreas.sandberg@arm.com 4411988Sandreas.sandberg@arm.comimport math 4511988Sandreas.sandberg@arm.comimport m5 4611988Sandreas.sandberg@arm.comfrom m5.objects import * 4711988Sandreas.sandberg@arm.comfrom m5.defines import buildEnv 4811988Sandreas.sandberg@arm.comfrom m5.util import addToPath, fatal 4911988Sandreas.sandberg@arm.com 5011988Sandreas.sandberg@arm.comfrom common import MemConfig 5111988Sandreas.sandberg@arm.com 5211988Sandreas.sandberg@arm.comfrom topologies import * 5311988Sandreas.sandberg@arm.comfrom network import Network 5411988Sandreas.sandberg@arm.com 5511988Sandreas.sandberg@arm.comdef define_options(parser): 5611988Sandreas.sandberg@arm.com # By default, ruby uses the simple timing cpu 5711988Sandreas.sandberg@arm.com parser.set_defaults(cpu_type="TimingSimpleCPU") 5811988Sandreas.sandberg@arm.com 5911988Sandreas.sandberg@arm.com parser.add_option("--ruby-clock", action="store", type="string", 6011988Sandreas.sandberg@arm.com default='2GHz', 6111988Sandreas.sandberg@arm.com help="Clock for blocks running at Ruby system's speed") 6211988Sandreas.sandberg@arm.com 6311988Sandreas.sandberg@arm.com parser.add_option("--access-backing-store", action="store_true", default=False, 6411988Sandreas.sandberg@arm.com help="Should ruby maintain a second copy of memory") 6511988Sandreas.sandberg@arm.com 6611988Sandreas.sandberg@arm.com # Options related to cache structure 6711988Sandreas.sandberg@arm.com parser.add_option("--ports", action="store", type="int", default=4, 6811988Sandreas.sandberg@arm.com help="used of transitions per cycle which is a proxy \ 6911988Sandreas.sandberg@arm.com for the number of ports.") 7011988Sandreas.sandberg@arm.com 7111988Sandreas.sandberg@arm.com # network options are in network/Network.py 7211988Sandreas.sandberg@arm.com 7311988Sandreas.sandberg@arm.com # ruby mapping options 7411988Sandreas.sandberg@arm.com parser.add_option("--numa-high-bit", type="int", default=0, 7511988Sandreas.sandberg@arm.com help="high order address bit to use for numa mapping. " \ 7611988Sandreas.sandberg@arm.com "0 = highest bit, not specified = lowest bit") 7711988Sandreas.sandberg@arm.com 7811988Sandreas.sandberg@arm.com parser.add_option("--recycle-latency", type="int", default=10, 7911988Sandreas.sandberg@arm.com help="Recycle latency for ruby controller input buffers") 8011988Sandreas.sandberg@arm.com 8111988Sandreas.sandberg@arm.com protocol = buildEnv['PROTOCOL'] 8211988Sandreas.sandberg@arm.com exec "import %s" % protocol 8311988Sandreas.sandberg@arm.com eval("%s.define_options(parser)" % protocol) 8411988Sandreas.sandberg@arm.com Network.define_options(parser) 8511988Sandreas.sandberg@arm.com 8611988Sandreas.sandberg@arm.comdef setup_memory_controllers(system, ruby, dir_cntrls, options): 8711988Sandreas.sandberg@arm.com ruby.block_size_bytes = options.cacheline_size 8811988Sandreas.sandberg@arm.com ruby.memory_size_bits = 48 8911988Sandreas.sandberg@arm.com 9011988Sandreas.sandberg@arm.com index = 0 9111988Sandreas.sandberg@arm.com mem_ctrls = [] 9211988Sandreas.sandberg@arm.com crossbars = [] 9311988Sandreas.sandberg@arm.com 9411988Sandreas.sandberg@arm.com # Sets bits to be used for interleaving. Creates memory controllers 9511988Sandreas.sandberg@arm.com # attached to a directory controller. A separate controller is created 9611988Sandreas.sandberg@arm.com # for each address range as the abstract memory can handle only one 9711988Sandreas.sandberg@arm.com # contiguous address range as of now. 9811988Sandreas.sandberg@arm.com for dir_cntrl in dir_cntrls: 9911988Sandreas.sandberg@arm.com crossbar = None 10011988Sandreas.sandberg@arm.com if len(system.mem_ranges) > 1: 10111988Sandreas.sandberg@arm.com crossbar = IOXBar() 10211988Sandreas.sandberg@arm.com crossbars.append(crossbar) 10311988Sandreas.sandberg@arm.com dir_cntrl.memory = crossbar.slave 10411988Sandreas.sandberg@arm.com 10511988Sandreas.sandberg@arm.com for r in system.mem_ranges: 10611988Sandreas.sandberg@arm.com mem_ctrl = MemConfig.create_mem_ctrl( 10711988Sandreas.sandberg@arm.com MemConfig.get(options.mem_type), r, index, options.num_dirs, 10811988Sandreas.sandberg@arm.com int(math.log(options.num_dirs, 2)), options.cacheline_size) 10911988Sandreas.sandberg@arm.com 11011988Sandreas.sandberg@arm.com if options.access_backing_store: 11111988Sandreas.sandberg@arm.com mem_ctrl.kvm_map=False 11211988Sandreas.sandberg@arm.com 11311988Sandreas.sandberg@arm.com mem_ctrls.append(mem_ctrl) 11411988Sandreas.sandberg@arm.com 11511988Sandreas.sandberg@arm.com if crossbar != None: 11611988Sandreas.sandberg@arm.com mem_ctrl.port = crossbar.master 11711988Sandreas.sandberg@arm.com else: 11811988Sandreas.sandberg@arm.com mem_ctrl.port = dir_cntrl.memory 11911988Sandreas.sandberg@arm.com 12011988Sandreas.sandberg@arm.com index += 1 12111988Sandreas.sandberg@arm.com 12211988Sandreas.sandberg@arm.com system.mem_ctrls = mem_ctrls 12311988Sandreas.sandberg@arm.com 12411988Sandreas.sandberg@arm.com if len(crossbars) > 0: 12511988Sandreas.sandberg@arm.com ruby.crossbars = crossbars 12611988Sandreas.sandberg@arm.com 12711988Sandreas.sandberg@arm.com 12811988Sandreas.sandberg@arm.comdef create_topology(controllers, options): 12911988Sandreas.sandberg@arm.com """ Called from create_system in configs/ruby/<protocol>.py 13011988Sandreas.sandberg@arm.com Must return an object which is a subclass of BaseTopology 13111988Sandreas.sandberg@arm.com found in configs/topologies/BaseTopology.py 13211988Sandreas.sandberg@arm.com This is a wrapper for the legacy topologies. 13311988Sandreas.sandberg@arm.com """ 13411988Sandreas.sandberg@arm.com exec "import topologies.%s as Topo" % options.topology 13511988Sandreas.sandberg@arm.com topology = eval("Topo.%s(controllers)" % options.topology) 13611988Sandreas.sandberg@arm.com return topology 13711988Sandreas.sandberg@arm.com 13811988Sandreas.sandberg@arm.comdef create_system(options, full_system, system, piobus = None, dma_ports = []): 13911988Sandreas.sandberg@arm.com 14011988Sandreas.sandberg@arm.com system.ruby = RubySystem() 14111988Sandreas.sandberg@arm.com ruby = system.ruby 14211988Sandreas.sandberg@arm.com 14311988Sandreas.sandberg@arm.com # Create the network object 14411988Sandreas.sandberg@arm.com (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 14511988Sandreas.sandberg@arm.com Network.create_network(options, ruby) 14611988Sandreas.sandberg@arm.com ruby.network = network 14711988Sandreas.sandberg@arm.com 14811988Sandreas.sandberg@arm.com protocol = buildEnv['PROTOCOL'] 14911988Sandreas.sandberg@arm.com exec "import %s" % protocol 15011988Sandreas.sandberg@arm.com try: 15111988Sandreas.sandberg@arm.com (cpu_sequencers, dir_cntrls, topology) = \ 15211988Sandreas.sandberg@arm.com eval("%s.create_system(options, full_system, system, dma_ports,\ 15311988Sandreas.sandberg@arm.com ruby)" 15411988Sandreas.sandberg@arm.com % protocol) 15511988Sandreas.sandberg@arm.com except: 15611988Sandreas.sandberg@arm.com print("Error: could not create sytem for ruby protocol %s" % protocol) 15711988Sandreas.sandberg@arm.com raise 15811988Sandreas.sandberg@arm.com 15911988Sandreas.sandberg@arm.com # Create the network topology 16011988Sandreas.sandberg@arm.com topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 16111988Sandreas.sandberg@arm.com RouterClass) 16211988Sandreas.sandberg@arm.com 16311988Sandreas.sandberg@arm.com # Initialize network based on topology 16411988Sandreas.sandberg@arm.com Network.init_network(options, network, InterfaceClass) 16511988Sandreas.sandberg@arm.com 16611988Sandreas.sandberg@arm.com # Create a port proxy for connecting the system port. This is 16711988Sandreas.sandberg@arm.com # independent of the protocol and kept in the protocol-agnostic 16811988Sandreas.sandberg@arm.com # part (i.e. here). 16911988Sandreas.sandberg@arm.com sys_port_proxy = RubyPortProxy(ruby_system = ruby) 17011988Sandreas.sandberg@arm.com if piobus is not None: 17111988Sandreas.sandberg@arm.com sys_port_proxy.pio_master_port = piobus.slave 17211988Sandreas.sandberg@arm.com 17311988Sandreas.sandberg@arm.com # Give the system port proxy a SimObject parent without creating a 17411988Sandreas.sandberg@arm.com # full-fledged controller 17511988Sandreas.sandberg@arm.com system.sys_port_proxy = sys_port_proxy 17611988Sandreas.sandberg@arm.com 17711988Sandreas.sandberg@arm.com # Connect the system port for loading of binaries etc 17811988Sandreas.sandberg@arm.com system.system_port = system.sys_port_proxy.slave 17911988Sandreas.sandberg@arm.com 18011988Sandreas.sandberg@arm.com setup_memory_controllers(system, ruby, dir_cntrls, options) 18111988Sandreas.sandberg@arm.com 18211988Sandreas.sandberg@arm.com # Connect the cpu sequencers and the piobus 18311988Sandreas.sandberg@arm.com if piobus != None: 18411988Sandreas.sandberg@arm.com for cpu_seq in cpu_sequencers: 18511988Sandreas.sandberg@arm.com cpu_seq.pio_master_port = piobus.slave 18611988Sandreas.sandberg@arm.com cpu_seq.mem_master_port = piobus.slave 18711988Sandreas.sandberg@arm.com 18811988Sandreas.sandberg@arm.com if buildEnv['TARGET_ISA'] == "x86": 18911988Sandreas.sandberg@arm.com cpu_seq.pio_slave_port = piobus.master 19011988Sandreas.sandberg@arm.com 19111988Sandreas.sandberg@arm.com ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 19211988Sandreas.sandberg@arm.com ruby._cpu_ports = cpu_sequencers 19311988Sandreas.sandberg@arm.com ruby.num_of_sequencers = len(cpu_sequencers) 19411988Sandreas.sandberg@arm.com 19511988Sandreas.sandberg@arm.com # Create a backing copy of physical memory in case required 19611988Sandreas.sandberg@arm.com if options.access_backing_store: 19711988Sandreas.sandberg@arm.com ruby.access_backing_store = True 19811988Sandreas.sandberg@arm.com ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 19911988Sandreas.sandberg@arm.com in_addr_map=False) 20011988Sandreas.sandberg@arm.com 20111988Sandreas.sandberg@arm.comdef create_directories(options, mem_ranges, ruby_system): 20211988Sandreas.sandberg@arm.com dir_cntrl_nodes = [] 20311988Sandreas.sandberg@arm.com if options.numa_high_bit: 20411988Sandreas.sandberg@arm.com numa_bit = options.numa_high_bit 20511988Sandreas.sandberg@arm.com else: 20611988Sandreas.sandberg@arm.com # if the numa_bit is not specified, set the directory bits as the 20711988Sandreas.sandberg@arm.com # lowest bits above the block offset bits, and the numa_bit as the 20811988Sandreas.sandberg@arm.com # highest of those directory bits 20911988Sandreas.sandberg@arm.com dir_bits = int(math.log(options.num_dirs, 2)) 21011988Sandreas.sandberg@arm.com block_size_bits = int(math.log(options.cacheline_size, 2)) 21111988Sandreas.sandberg@arm.com numa_bit = block_size_bits + dir_bits - 1 21211988Sandreas.sandberg@arm.com 21311988Sandreas.sandberg@arm.com for i in xrange(options.num_dirs): 21411988Sandreas.sandberg@arm.com dir_ranges = [] 21511988Sandreas.sandberg@arm.com for r in mem_ranges: 21611988Sandreas.sandberg@arm.com addr_range = m5.objects.AddrRange(r.start, size = r.size(), 21711988Sandreas.sandberg@arm.com intlvHighBit = numa_bit, 21811988Sandreas.sandberg@arm.com intlvBits = dir_bits, 21911988Sandreas.sandberg@arm.com intlvMatch = i) 22011988Sandreas.sandberg@arm.com dir_ranges.append(addr_range) 22111988Sandreas.sandberg@arm.com 22211988Sandreas.sandberg@arm.com dir_cntrl = Directory_Controller() 22311988Sandreas.sandberg@arm.com dir_cntrl.version = i 22411988Sandreas.sandberg@arm.com dir_cntrl.directory = RubyDirectoryMemory() 22511988Sandreas.sandberg@arm.com dir_cntrl.ruby_system = ruby_system 22611988Sandreas.sandberg@arm.com dir_cntrl.addr_ranges = dir_ranges 22711988Sandreas.sandberg@arm.com 22811988Sandreas.sandberg@arm.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 22911988Sandreas.sandberg@arm.com dir_cntrl_nodes.append(dir_cntrl) 23011988Sandreas.sandberg@arm.com return dir_cntrl_nodes 23111988Sandreas.sandberg@arm.com 23211988Sandreas.sandberg@arm.comdef send_evicts(options): 23311988Sandreas.sandberg@arm.com # currently, 2 scenarios warrant forwarding evictions to the CPU: 23411988Sandreas.sandberg@arm.com # 1. The O3 model must keep the LSQ coherent with the caches 23511988Sandreas.sandberg@arm.com # 2. The x86 mwait instruction is built on top of coherence invalidations 23611988Sandreas.sandberg@arm.com # 3. The local exclusive monitor in ARM systems 23711988Sandreas.sandberg@arm.com if options.cpu_type == "DerivO3CPU" or \ 23811988Sandreas.sandberg@arm.com buildEnv['TARGET_ISA'] in ('x86', 'arm'): 23911988Sandreas.sandberg@arm.com return True 24011988Sandreas.sandberg@arm.com return False 24111988Sandreas.sandberg@arm.com