Ruby.py revision 12065
11689SN/A# Copyright (c) 2012, 2017 ARM Limited 22329SN/A# All rights reserved. 31689SN/A# 41689SN/A# The license below extends only to copyright in the software and shall 51689SN/A# not be construed as granting a license to any other intellectual 61689SN/A# property including but not limited to intellectual property relating 71689SN/A# to a hardware implementation of the functionality of the software 81689SN/A# licensed hereunder. You may use the software subject to the license 91689SN/A# terms below provided that you ensure that this notice is replicated 101689SN/A# unmodified and in its entirety in all distributions of the software, 111689SN/A# modified or unmodified, in source code or in binary form. 121689SN/A# 131689SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 141689SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 151689SN/A# All rights reserved. 161689SN/A# 171689SN/A# Redistribution and use in source and binary forms, with or without 181689SN/A# modification, are permitted provided that the following conditions are 191689SN/A# met: redistributions of source code must retain the above copyright 201689SN/A# notice, this list of conditions and the following disclaimer; 211689SN/A# redistributions in binary form must reproduce the above copyright 221689SN/A# notice, this list of conditions and the following disclaimer in the 231689SN/A# documentation and/or other materials provided with the distribution; 241689SN/A# neither the name of the copyright holders nor the names of its 251689SN/A# contributors may be used to endorse or promote products derived from 261689SN/A# this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311858SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321717SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331060SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361061SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392292SN/A# 401060SN/A# Authors: Brad Beckmann 411060SN/A 421060SN/Aimport math 432292SN/Aimport m5 442292SN/Afrom m5.objects import * 451060SN/Afrom m5.defines import buildEnv 462292SN/Afrom m5.util import addToPath, fatal 472292SN/A 482292SN/Afrom common import MemConfig 492292SN/A 502292SN/Afrom topologies import * 512292SN/Afrom network import Network 522292SN/A 532292SN/Adef define_options(parser): 542292SN/A # By default, ruby uses the simple timing cpu 552292SN/A parser.set_defaults(cpu_type="TimingSimpleCPU") 562292SN/A 572292SN/A parser.add_option("--ruby-clock", action="store", type="string", 582292SN/A default='2GHz', 592292SN/A help="Clock for blocks running at Ruby system's speed") 602292SN/A 612292SN/A parser.add_option("--access-backing-store", action="store_true", default=False, 622292SN/A help="Should ruby maintain a second copy of memory") 632292SN/A 642292SN/A # Options related to cache structure 652292SN/A parser.add_option("--ports", action="store", type="int", default=4, 662292SN/A help="used of transitions per cycle which is a proxy \ 672292SN/A for the number of ports.") 682292SN/A 692292SN/A # network options are in network/Network.py 702292SN/A 712292SN/A # ruby mapping options 722292SN/A parser.add_option("--numa-high-bit", type="int", default=0, 732292SN/A help="high order address bit to use for numa mapping. " \ 742292SN/A "0 = highest bit, not specified = lowest bit") 752292SN/A 762292SN/A parser.add_option("--recycle-latency", type="int", default=10, 772292SN/A help="Recycle latency for ruby controller input buffers") 782292SN/A 792292SN/A protocol = buildEnv['PROTOCOL'] 802292SN/A exec "import %s" % protocol 812292SN/A eval("%s.define_options(parser)" % protocol) 822292SN/A Network.define_options(parser) 832292SN/A 842292SN/Adef setup_memory_controllers(system, ruby, dir_cntrls, options): 852292SN/A ruby.block_size_bytes = options.cacheline_size 862292SN/A ruby.memory_size_bits = 48 872292SN/A 882292SN/A index = 0 892292SN/A mem_ctrls = [] 902292SN/A crossbars = [] 912292SN/A 922292SN/A # Sets bits to be used for interleaving. Creates memory controllers 932292SN/A # attached to a directory controller. A separate controller is created 942292SN/A # for each address range as the abstract memory can handle only one 952292SN/A # contiguous address range as of now. 962292SN/A for dir_cntrl in dir_cntrls: 972292SN/A crossbar = None 982292SN/A if len(system.mem_ranges) > 1: 991060SN/A crossbar = IOXBar() 1001060SN/A crossbars.append(crossbar) 1011061SN/A dir_cntrl.memory = crossbar.slave 1021060SN/A 1031060SN/A for r in system.mem_ranges: 1041060SN/A mem_ctrl = MemConfig.create_mem_ctrl( 1051060SN/A MemConfig.get(options.mem_type), r, index, options.num_dirs, 1061060SN/A int(math.log(options.num_dirs, 2)), options.cacheline_size) 1072292SN/A 1082292SN/A if options.access_backing_store: 1092292SN/A mem_ctrl.kvm_map=False 1102292SN/A 1111060SN/A mem_ctrls.append(mem_ctrl) 1122292SN/A 1132292SN/A if crossbar != None: 1142292SN/A mem_ctrl.port = crossbar.master 1152292SN/A else: 1162292SN/A mem_ctrl.port = dir_cntrl.memory 1172292SN/A 1182292SN/A index += 1 1192292SN/A 1202292SN/A system.mem_ctrls = mem_ctrls 1212292SN/A 1222292SN/A if len(crossbars) > 0: 1232292SN/A ruby.crossbars = crossbars 1242292SN/A 1252292SN/A 1262307SN/Adef create_topology(controllers, options): 1272307SN/A """ Called from create_system in configs/ruby/<protocol>.py 1282307SN/A Must return an object which is a subclass of BaseTopology 1292307SN/A found in configs/topologies/BaseTopology.py 1302307SN/A This is a wrapper for the legacy topologies. 1312307SN/A """ 1322307SN/A exec "import topologies.%s as Topo" % options.topology 1332307SN/A topology = eval("Topo.%s(controllers)" % options.topology) 1342307SN/A return topology 1352307SN/A 1362307SN/Adef create_system(options, full_system, system, piobus = None, dma_ports = []): 1372307SN/A 1382307SN/A system.ruby = RubySystem() 1392307SN/A ruby = system.ruby 1402307SN/A 1412307SN/A # Create the network object 1422307SN/A (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 1432307SN/A Network.create_network(options, ruby) 1442307SN/A ruby.network = network 1452307SN/A 1462307SN/A protocol = buildEnv['PROTOCOL'] 1472307SN/A exec "import %s" % protocol 1482307SN/A try: 1492307SN/A (cpu_sequencers, dir_cntrls, topology) = \ 1502307SN/A eval("%s.create_system(options, full_system, system, dma_ports,\ 1512292SN/A ruby)" 1522292SN/A % protocol) 1532292SN/A except: 1542292SN/A print "Error: could not create sytem for ruby protocol %s" % protocol 1552292SN/A raise 1562292SN/A 1572292SN/A # Create the network topology 1582292SN/A topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 1592292SN/A RouterClass) 1602292SN/A 1612292SN/A # Initialize network based on topology 1622292SN/A Network.init_network(options, network, InterfaceClass) 1632292SN/A 1642292SN/A # Create a port proxy for connecting the system port. This is 1652292SN/A # independent of the protocol and kept in the protocol-agnostic 1662292SN/A # part (i.e. here). 1672292SN/A sys_port_proxy = RubyPortProxy(ruby_system = ruby) 1682292SN/A if piobus is not None: 1692292SN/A sys_port_proxy.pio_master_port = piobus.slave 1702292SN/A 1712292SN/A # Give the system port proxy a SimObject parent without creating a 1722292SN/A # full-fledged controller 1732292SN/A system.sys_port_proxy = sys_port_proxy 1742292SN/A 1752292SN/A # Connect the system port for loading of binaries etc 1762292SN/A system.system_port = system.sys_port_proxy.slave 1772292SN/A 1782292SN/A setup_memory_controllers(system, ruby, dir_cntrls, options) 1792292SN/A 1802292SN/A # Connect the cpu sequencers and the piobus 1811060SN/A if piobus != None: 1821060SN/A for cpu_seq in cpu_sequencers: 1831061SN/A cpu_seq.pio_master_port = piobus.slave 1841060SN/A cpu_seq.mem_master_port = piobus.slave 1851060SN/A 1861060SN/A if buildEnv['TARGET_ISA'] == "x86": 1872292SN/A cpu_seq.pio_slave_port = piobus.master 1881061SN/A 1892292SN/A ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 1902292SN/A ruby._cpu_ports = cpu_sequencers 1911060SN/A ruby.num_of_sequencers = len(cpu_sequencers) 1922292SN/A 1932292SN/A # Create a backing copy of physical memory in case required 1941060SN/A if options.access_backing_store: 1952292SN/A ruby.access_backing_store = True 1962292SN/A ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 1972292SN/A in_addr_map=False) 1982292SN/A 1992292SN/Adef create_directories(options, mem_ranges, ruby_system): 2001060SN/A dir_cntrl_nodes = [] 2011060SN/A if options.numa_high_bit: 2021061SN/A numa_bit = options.numa_high_bit 2031060SN/A else: 2041061SN/A # if the numa_bit is not specified, set the directory bits as the 2051060SN/A # lowest bits above the block offset bits, and the numa_bit as the 2062292SN/A # highest of those directory bits 2071060SN/A dir_bits = int(math.log(options.num_dirs, 2)) 2081060SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 2092292SN/A numa_bit = block_size_bits + dir_bits - 1 2101060SN/A 2111060SN/A for i in xrange(options.num_dirs): 2121060SN/A dir_ranges = [] 2132292SN/A for r in mem_ranges: 2141060SN/A addr_range = m5.objects.AddrRange(r.start, size = r.size(), 2152292SN/A intlvHighBit = numa_bit, 2162292SN/A intlvBits = dir_bits, 2172292SN/A intlvMatch = i) 2182292SN/A dir_ranges.append(addr_range) 2192292SN/A 2202292SN/A dir_cntrl = Directory_Controller() 2211060SN/A dir_cntrl.version = i 2221060SN/A dir_cntrl.directory = RubyDirectoryMemory() 2232292SN/A dir_cntrl.ruby_system = ruby_system 2242292SN/A dir_cntrl.addr_ranges = dir_ranges 2252292SN/A 2262292SN/A exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 2272292SN/A dir_cntrl_nodes.append(dir_cntrl) 2282292SN/A return dir_cntrl_nodes 2292292SN/A 2302292SN/Adef send_evicts(options): 2312292SN/A # currently, 2 scenarios warrant forwarding evictions to the CPU: 2322292SN/A # 1. The O3 model must keep the LSQ coherent with the caches 2331060SN/A # 2. The x86 mwait instruction is built on top of coherence invalidations 2341060SN/A if options.cpu_type == "DerivO3CPU" or buildEnv['TARGET_ISA'] == 'x86': 2352292SN/A return True 2361060SN/A return False 2371060SN/A