Ruby.py revision 12014
12330SN/A# Copyright (c) 2012 ARM Limited 22330SN/A# All rights reserved. 32330SN/A# 42330SN/A# The license below extends only to copyright in the software and shall 52330SN/A# not be construed as granting a license to any other intellectual 62330SN/A# property including but not limited to intellectual property relating 72330SN/A# to a hardware implementation of the functionality of the software 82330SN/A# licensed hereunder. You may use the software subject to the license 92330SN/A# terms below provided that you ensure that this notice is replicated 102330SN/A# unmodified and in its entirety in all distributions of the software, 112330SN/A# modified or unmodified, in source code or in binary form. 122330SN/A# 132330SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 142330SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 152330SN/A# All rights reserved. 162330SN/A# 172330SN/A# Redistribution and use in source and binary forms, with or without 182330SN/A# modification, are permitted provided that the following conditions are 192330SN/A# met: redistributions of source code must retain the above copyright 202330SN/A# notice, this list of conditions and the following disclaimer; 212330SN/A# redistributions in binary form must reproduce the above copyright 222330SN/A# notice, this list of conditions and the following disclaimer in the 232330SN/A# documentation and/or other materials provided with the distribution; 242330SN/A# neither the name of the copyright holders nor the names of its 252330SN/A# contributors may be used to endorse or promote products derived from 262330SN/A# this software without specific prior written permission. 272689Sktlim@umich.edu# 282689Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292330SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342980Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352362SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362680Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382678Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392683Sktlim@umich.edu# 402683Sktlim@umich.edu# Authors: Brad Beckmann 412678Sktlim@umich.edu 422678Sktlim@umich.eduimport math 432292SN/Aimport m5 442292SN/Afrom m5.objects import * 452292SN/Afrom m5.defines import buildEnv 462292SN/Afrom m5.util import addToPath, fatal 473548Sgblack@eecs.umich.edu 483548Sgblack@eecs.umich.edufrom common import MemConfig 493548Sgblack@eecs.umich.edu 503548Sgblack@eecs.umich.edufrom topologies import * 512330SN/Afrom network import Network 522292SN/A 532292SN/Adef define_options(parser): 543402Sktlim@umich.edu # By default, ruby uses the simple timing cpu 552862Sktlim@umich.edu parser.set_defaults(cpu_type="TimingSimpleCPU") 563486Sktlim@umich.edu 573402Sktlim@umich.edu parser.add_option("--ruby-clock", action="store", type="string", 582862Sktlim@umich.edu default='2GHz', 592330SN/A help="Clock for blocks running at Ruby system's speed") 602330SN/A 612330SN/A parser.add_option("--access-backing-store", action="store_true", default=False, 622330SN/A help="Should ruby maintain a second copy of memory") 632330SN/A 642330SN/A # Options related to cache structure 652292SN/A parser.add_option("--ports", action="store", type="int", default=4, 662683Sktlim@umich.edu help="used of transitions per cycle which is a proxy \ 672683Sktlim@umich.edu for the number of ports.") 682292SN/A 693402Sktlim@umich.edu # network options are in network/Network.py 702292SN/A 713402Sktlim@umich.edu # ruby mapping options 723402Sktlim@umich.edu parser.add_option("--numa-high-bit", type="int", default=0, 732292SN/A help="high order address bit to use for numa mapping. " \ 742683Sktlim@umich.edu "0 = highest bit, not specified = lowest bit") 753486Sktlim@umich.edu 763486Sktlim@umich.edu parser.add_option("--recycle-latency", type="int", default=10, 772862Sktlim@umich.edu help="Recycle latency for ruby controller input buffers") 782862Sktlim@umich.edu 792862Sktlim@umich.edu protocol = buildEnv['PROTOCOL'] 802862Sktlim@umich.edu exec "import %s" % protocol 812683Sktlim@umich.edu eval("%s.define_options(parser)" % protocol) 822683Sktlim@umich.edu Network.define_options(parser) 832683Sktlim@umich.edu 842683Sktlim@umich.edudef setup_memory_controllers(system, ruby, dir_cntrls, options): 852683Sktlim@umich.edu ruby.block_size_bytes = options.cacheline_size 862683Sktlim@umich.edu ruby.memory_size_bits = 48 872683Sktlim@umich.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 882683Sktlim@umich.edu 892683Sktlim@umich.edu if options.numa_high_bit: 902683Sktlim@umich.edu numa_bit = options.numa_high_bit 912683Sktlim@umich.edu else: 922683Sktlim@umich.edu # if the numa_bit is not specified, set the directory bits as the 932683Sktlim@umich.edu # lowest bits above the block offset bits, and the numa_bit as the 945497Ssaidi@eecs.umich.edu # highest of those directory bits 953675Sktlim@umich.edu dir_bits = int(math.log(options.num_dirs, 2)) 963686Sktlim@umich.edu numa_bit = block_size_bits + dir_bits - 1 973675Sktlim@umich.edu 985497Ssaidi@eecs.umich.edu index = 0 993675Sktlim@umich.edu mem_ctrls = [] 1002683Sktlim@umich.edu crossbars = [] 1012683Sktlim@umich.edu 1022683Sktlim@umich.edu # Sets bits to be used for interleaving. Creates memory controllers 1032683Sktlim@umich.edu # attached to a directory controller. A separate controller is created 1042683Sktlim@umich.edu # for each address range as the abstract memory can handle only one 1052683Sktlim@umich.edu # contiguous address range as of now. 1062683Sktlim@umich.edu for dir_cntrl in dir_cntrls: 1072683Sktlim@umich.edu dir_cntrl.directory.numa_high_bit = numa_bit 1083548Sgblack@eecs.umich.edu 1092683Sktlim@umich.edu crossbar = None 1102690Sktlim@umich.edu if len(system.mem_ranges) > 1: 1112690Sktlim@umich.edu crossbar = IOXBar() 1122683Sktlim@umich.edu crossbars.append(crossbar) 1132683Sktlim@umich.edu dir_cntrl.memory = crossbar.slave 1145499Ssaidi@eecs.umich.edu 1152683Sktlim@umich.edu for r in system.mem_ranges: 1162683Sktlim@umich.edu mem_ctrl = MemConfig.create_mem_ctrl( 1172683Sktlim@umich.edu MemConfig.get(options.mem_type), r, index, options.num_dirs, 1183402Sktlim@umich.edu int(math.log(options.num_dirs, 2)), options.cacheline_size) 1192683Sktlim@umich.edu 1202683Sktlim@umich.edu if options.access_backing_store: 1212683Sktlim@umich.edu mem_ctrl.kvm_map=False 1222683Sktlim@umich.edu 1232683Sktlim@umich.edu mem_ctrls.append(mem_ctrl) 1242678Sktlim@umich.edu 1252292SN/A if crossbar != None: 1262683Sktlim@umich.edu mem_ctrl.port = crossbar.master 1272683Sktlim@umich.edu else: 1282292SN/A mem_ctrl.port = dir_cntrl.memory 1292683Sktlim@umich.edu 1302683Sktlim@umich.edu index += 1 1312683Sktlim@umich.edu 1322683Sktlim@umich.edu system.mem_ctrls = mem_ctrls 1332683Sktlim@umich.edu 1342683Sktlim@umich.edu if len(crossbars) > 0: 1352683Sktlim@umich.edu ruby.crossbars = crossbars 1362683Sktlim@umich.edu 1372683Sktlim@umich.edu 1382683Sktlim@umich.edudef create_topology(controllers, options): 1392683Sktlim@umich.edu """ Called from create_system in configs/ruby/<protocol>.py 1402683Sktlim@umich.edu Must return an object which is a subclass of BaseTopology 1412683Sktlim@umich.edu found in configs/topologies/BaseTopology.py 1422683Sktlim@umich.edu This is a wrapper for the legacy topologies. 1432683Sktlim@umich.edu """ 1442683Sktlim@umich.edu exec "import topologies.%s as Topo" % options.topology 1452683Sktlim@umich.edu topology = eval("Topo.%s(controllers)" % options.topology) 1462683Sktlim@umich.edu return topology 1472683Sktlim@umich.edu 1483673Srdreslin@umich.edudef create_system(options, full_system, system, piobus = None, dma_ports = []): 1493675Sktlim@umich.edu 1503675Sktlim@umich.edu system.ruby = RubySystem() 1513675Sktlim@umich.edu ruby = system.ruby 1523486Sktlim@umich.edu 1532683Sktlim@umich.edu # Create the network object 1542683Sktlim@umich.edu (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 1552683Sktlim@umich.edu Network.create_network(options, ruby) 1562683Sktlim@umich.edu ruby.network = network 1572683Sktlim@umich.edu 1582683Sktlim@umich.edu protocol = buildEnv['PROTOCOL'] 1592683Sktlim@umich.edu exec "import %s" % protocol 1602683Sktlim@umich.edu try: 1612683Sktlim@umich.edu (cpu_sequencers, dir_cntrls, topology) = \ 1622683Sktlim@umich.edu eval("%s.create_system(options, full_system, system, dma_ports,\ 1632683Sktlim@umich.edu ruby)" 1642683Sktlim@umich.edu % protocol) 1652683Sktlim@umich.edu except: 1662683Sktlim@umich.edu print "Error: could not create sytem for ruby protocol %s" % protocol 1672683Sktlim@umich.edu raise 1682683Sktlim@umich.edu 1692683Sktlim@umich.edu # Create the network topology 1702683Sktlim@umich.edu topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 1713402Sktlim@umich.edu RouterClass) 1723402Sktlim@umich.edu 1733402Sktlim@umich.edu # Initialize network based on topology 1742683Sktlim@umich.edu Network.init_network(options, network, InterfaceClass) 1752683Sktlim@umich.edu 1762292SN/A # Create a port proxy for connecting the system port. This is 1772292SN/A # independent of the protocol and kept in the protocol-agnostic 1782292SN/A # part (i.e. here). 1792292SN/A sys_port_proxy = RubyPortProxy(ruby_system = ruby) 1802292SN/A if piobus is not None: 1812690Sktlim@umich.edu sys_port_proxy.pio_master_port = piobus.slave 1822683Sktlim@umich.edu 1832683Sktlim@umich.edu # Give the system port proxy a SimObject parent without creating a 1842292SN/A # full-fledged controller 1852683Sktlim@umich.edu system.sys_port_proxy = sys_port_proxy 1862683Sktlim@umich.edu 1872292SN/A # Connect the system port for loading of binaries etc 1882292SN/A system.system_port = system.sys_port_proxy.slave 1892683Sktlim@umich.edu 1902292SN/A setup_memory_controllers(system, ruby, dir_cntrls, options) 1912292SN/A 1922292SN/A # Connect the cpu sequencers and the piobus 1932292SN/A if piobus != None: 1942292SN/A for cpu_seq in cpu_sequencers: 1953548Sgblack@eecs.umich.edu cpu_seq.pio_master_port = piobus.slave 1962683Sktlim@umich.edu cpu_seq.mem_master_port = piobus.slave 1972683Sktlim@umich.edu 1982683Sktlim@umich.edu if buildEnv['TARGET_ISA'] == "x86": 1992683Sktlim@umich.edu cpu_seq.pio_slave_port = piobus.master 2002683Sktlim@umich.edu 2012683Sktlim@umich.edu ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 2025497Ssaidi@eecs.umich.edu ruby._cpu_ports = cpu_sequencers 2032683Sktlim@umich.edu ruby.num_of_sequencers = len(cpu_sequencers) 2042292SN/A 2052678Sktlim@umich.edu # Create a backing copy of physical memory in case required 2062678Sktlim@umich.edu if options.access_backing_store: 2072292SN/A ruby.access_backing_store = True 2082292SN/A ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 2092292SN/A in_addr_map=False) 2102292SN/A 2112292SN/Adef send_evicts(options): 2122292SN/A # currently, 2 scenarios warrant forwarding evictions to the CPU: 2132330SN/A # 1. The O3 model must keep the LSQ coherent with the caches 2142330SN/A # 2. The x86 mwait instruction is built on top of coherence invalidations 2152330SN/A if options.cpu_type == "DerivO3CPU" or buildEnv['TARGET_ISA'] == 'x86': 2162683Sktlim@umich.edu return True 2172683Sktlim@umich.edu return False 2182683Sktlim@umich.edu