Ruby.py revision 11670
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 136892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 146892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 156892SBrad.Beckmann@amd.com# All rights reserved. 166892SBrad.Beckmann@amd.com# 176892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 186892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 196892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 206892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 216892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 226892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 236892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 246892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 256892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 266892SBrad.Beckmann@amd.com# this software without specific prior written permission. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396892SBrad.Beckmann@amd.com# 406892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 416892SBrad.Beckmann@amd.com 427563SBrad.Beckmann@amd.comimport math 436892SBrad.Beckmann@amd.comimport m5 446892SBrad.Beckmann@amd.comfrom m5.objects import * 456892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 4610118Snilay@cs.wisc.edufrom m5.util import addToPath, fatal 4710118Snilay@cs.wisc.edu 4810524Snilay@cs.wisc.eduimport MemConfig 4911662Stushar@ece.gatech.edu 5011670Sandreas.hansson@arm.comfrom topologies import * 5111670Sandreas.hansson@arm.comfrom network import Network 526892SBrad.Beckmann@amd.com 537538SBrad.Beckmann@amd.comdef define_options(parser): 548939SBrad.Beckmann@amd.com # By default, ruby uses the simple timing cpu 558939SBrad.Beckmann@amd.com parser.set_defaults(cpu_type="timing") 568939SBrad.Beckmann@amd.com 579791Sakash.bagdia@arm.com parser.add_option("--ruby-clock", action="store", type="string", 589791Sakash.bagdia@arm.com default='2GHz', 599791Sakash.bagdia@arm.com help="Clock for blocks running at Ruby system's speed") 609791Sakash.bagdia@arm.com 6110525Snilay@cs.wisc.edu parser.add_option("--access-backing-store", action="store_true", default=False, 6210525Snilay@cs.wisc.edu help="Should ruby maintain a second copy of memory") 6310525Snilay@cs.wisc.edu 649841Snilay@cs.wisc.edu # Options related to cache structure 659841Snilay@cs.wisc.edu parser.add_option("--ports", action="store", type="int", default=4, 669841Snilay@cs.wisc.edu help="used of transitions per cycle which is a proxy \ 679841Snilay@cs.wisc.edu for the number of ports.") 689841Snilay@cs.wisc.edu 6911662Stushar@ece.gatech.edu # network options are in network/Network.py 707538SBrad.Beckmann@amd.com 717538SBrad.Beckmann@amd.com # ruby mapping options 727917SBrad.Beckmann@amd.com parser.add_option("--numa-high-bit", type="int", default=0, 737563SBrad.Beckmann@amd.com help="high order address bit to use for numa mapping. " \ 747563SBrad.Beckmann@amd.com "0 = highest bit, not specified = lowest bit") 757538SBrad.Beckmann@amd.com 767566SBrad.Beckmann@amd.com parser.add_option("--recycle-latency", type="int", default=10, 777566SBrad.Beckmann@amd.com help="Recycle latency for ruby controller input buffers") 787809Snilay@cs.wisc.edu 797538SBrad.Beckmann@amd.com protocol = buildEnv['PROTOCOL'] 807538SBrad.Beckmann@amd.com exec "import %s" % protocol 817538SBrad.Beckmann@amd.com eval("%s.define_options(parser)" % protocol) 8211670Sandreas.hansson@arm.com Network.define_options(parser) 837538SBrad.Beckmann@amd.com 8410524Snilay@cs.wisc.edudef setup_memory_controllers(system, ruby, dir_cntrls, options): 8510524Snilay@cs.wisc.edu ruby.block_size_bytes = options.cacheline_size 8610524Snilay@cs.wisc.edu ruby.memory_size_bits = 48 8710524Snilay@cs.wisc.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 8810524Snilay@cs.wisc.edu 8910524Snilay@cs.wisc.edu if options.numa_high_bit: 9010524Snilay@cs.wisc.edu numa_bit = options.numa_high_bit 9110524Snilay@cs.wisc.edu else: 9210524Snilay@cs.wisc.edu # if the numa_bit is not specified, set the directory bits as the 9310524Snilay@cs.wisc.edu # lowest bits above the block offset bits, and the numa_bit as the 9410524Snilay@cs.wisc.edu # highest of those directory bits 9510524Snilay@cs.wisc.edu dir_bits = int(math.log(options.num_dirs, 2)) 9610524Snilay@cs.wisc.edu numa_bit = block_size_bits + dir_bits - 1 9710524Snilay@cs.wisc.edu 9810524Snilay@cs.wisc.edu index = 0 9910524Snilay@cs.wisc.edu mem_ctrls = [] 10010524Snilay@cs.wisc.edu crossbars = [] 10110524Snilay@cs.wisc.edu 10210524Snilay@cs.wisc.edu # Sets bits to be used for interleaving. Creates memory controllers 10310524Snilay@cs.wisc.edu # attached to a directory controller. A separate controller is created 10410524Snilay@cs.wisc.edu # for each address range as the abstract memory can handle only one 10510524Snilay@cs.wisc.edu # contiguous address range as of now. 10610524Snilay@cs.wisc.edu for dir_cntrl in dir_cntrls: 10710524Snilay@cs.wisc.edu dir_cntrl.directory.numa_high_bit = numa_bit 10810524Snilay@cs.wisc.edu 10910524Snilay@cs.wisc.edu crossbar = None 11010524Snilay@cs.wisc.edu if len(system.mem_ranges) > 1: 11110720Sandreas.hansson@arm.com crossbar = IOXBar() 11210524Snilay@cs.wisc.edu crossbars.append(crossbar) 11310524Snilay@cs.wisc.edu dir_cntrl.memory = crossbar.slave 11410524Snilay@cs.wisc.edu 11510524Snilay@cs.wisc.edu for r in system.mem_ranges: 11610524Snilay@cs.wisc.edu mem_ctrl = MemConfig.create_mem_ctrl( 11710524Snilay@cs.wisc.edu MemConfig.get(options.mem_type), r, index, options.num_dirs, 11810524Snilay@cs.wisc.edu int(math.log(options.num_dirs, 2)), options.cacheline_size) 11910524Snilay@cs.wisc.edu 12011616Sdavid.j.hashe@gmail.com if options.access_backing_store: 12111616Sdavid.j.hashe@gmail.com mem_ctrl.kvm_map=False 12211616Sdavid.j.hashe@gmail.com 12310524Snilay@cs.wisc.edu mem_ctrls.append(mem_ctrl) 12410524Snilay@cs.wisc.edu 12510524Snilay@cs.wisc.edu if crossbar != None: 12610524Snilay@cs.wisc.edu mem_ctrl.port = crossbar.master 12710524Snilay@cs.wisc.edu else: 12810524Snilay@cs.wisc.edu mem_ctrl.port = dir_cntrl.memory 12910524Snilay@cs.wisc.edu 13010524Snilay@cs.wisc.edu index += 1 13110524Snilay@cs.wisc.edu 13210524Snilay@cs.wisc.edu system.mem_ctrls = mem_ctrls 13310524Snilay@cs.wisc.edu 13410524Snilay@cs.wisc.edu if len(crossbars) > 0: 13510524Snilay@cs.wisc.edu ruby.crossbars = crossbars 13610524Snilay@cs.wisc.edu 13710524Snilay@cs.wisc.edu 1389100SBrad.Beckmann@amd.comdef create_topology(controllers, options): 1399100SBrad.Beckmann@amd.com """ Called from create_system in configs/ruby/<protocol>.py 1409100SBrad.Beckmann@amd.com Must return an object which is a subclass of BaseTopology 1419100SBrad.Beckmann@amd.com found in configs/topologies/BaseTopology.py 1429100SBrad.Beckmann@amd.com This is a wrapper for the legacy topologies. 1439100SBrad.Beckmann@amd.com """ 14411670Sandreas.hansson@arm.com exec "import topologies.%s as Topo" % options.topology 1459100SBrad.Beckmann@amd.com topology = eval("Topo.%s(controllers)" % options.topology) 1469100SBrad.Beckmann@amd.com return topology 1479100SBrad.Beckmann@amd.com 14810519Snilay@cs.wisc.edudef create_system(options, full_system, system, piobus = None, dma_ports = []): 1496892SBrad.Beckmann@amd.com 15010524Snilay@cs.wisc.edu system.ruby = RubySystem() 1518436SBrad.Beckmann@amd.com ruby = system.ruby 1528436SBrad.Beckmann@amd.com 15311662Stushar@ece.gatech.edu # Create the network object 15411662Stushar@ece.gatech.edu (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \ 15511662Stushar@ece.gatech.edu Network.create_network(options, ruby) 15610311Snilay@cs.wisc.edu ruby.network = network 15710311Snilay@cs.wisc.edu 15810551Ssteve.reinhardt@amd.com protocol = buildEnv['PROTOCOL'] 15910551Ssteve.reinhardt@amd.com exec "import %s" % protocol 16010311Snilay@cs.wisc.edu try: 16110311Snilay@cs.wisc.edu (cpu_sequencers, dir_cntrls, topology) = \ 16210551Ssteve.reinhardt@amd.com eval("%s.create_system(options, full_system, system, dma_ports,\ 16310551Ssteve.reinhardt@amd.com ruby)" 16410551Ssteve.reinhardt@amd.com % protocol) 16510311Snilay@cs.wisc.edu except: 16610551Ssteve.reinhardt@amd.com print "Error: could not create sytem for ruby protocol %s" % protocol 16710311Snilay@cs.wisc.edu raise 16810311Snilay@cs.wisc.edu 16911662Stushar@ece.gatech.edu # Create the network topology 17011662Stushar@ece.gatech.edu topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 17111662Stushar@ece.gatech.edu RouterClass) 17211662Stushar@ece.gatech.edu 17311662Stushar@ece.gatech.edu # Initialize network based on topology 17411662Stushar@ece.gatech.edu Network.init_network(options, network, InterfaceClass) 17511662Stushar@ece.gatech.edu 17610311Snilay@cs.wisc.edu # Create a port proxy for connecting the system port. This is 17710311Snilay@cs.wisc.edu # independent of the protocol and kept in the protocol-agnostic 17810311Snilay@cs.wisc.edu # part (i.e. here). 17910311Snilay@cs.wisc.edu sys_port_proxy = RubyPortProxy(ruby_system = ruby) 18011596Sandreas.sandberg@arm.com if piobus is not None: 18111596Sandreas.sandberg@arm.com sys_port_proxy.pio_master_port = piobus.slave 18210311Snilay@cs.wisc.edu 18310311Snilay@cs.wisc.edu # Give the system port proxy a SimObject parent without creating a 18410311Snilay@cs.wisc.edu # full-fledged controller 18510311Snilay@cs.wisc.edu system.sys_port_proxy = sys_port_proxy 18610311Snilay@cs.wisc.edu 18710311Snilay@cs.wisc.edu # Connect the system port for loading of binaries etc 18810311Snilay@cs.wisc.edu system.system_port = system.sys_port_proxy.slave 1899148Spowerjg@cs.wisc.edu 19010524Snilay@cs.wisc.edu setup_memory_controllers(system, ruby, dir_cntrls, options) 19110116Snilay@cs.wisc.edu 19210116Snilay@cs.wisc.edu # Connect the cpu sequencers and the piobus 19310116Snilay@cs.wisc.edu if piobus != None: 19410116Snilay@cs.wisc.edu for cpu_seq in cpu_sequencers: 19510116Snilay@cs.wisc.edu cpu_seq.pio_master_port = piobus.slave 19610116Snilay@cs.wisc.edu cpu_seq.mem_master_port = piobus.slave 19710116Snilay@cs.wisc.edu 19810116Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 19910116Snilay@cs.wisc.edu cpu_seq.pio_slave_port = piobus.master 20010116Snilay@cs.wisc.edu 20111172Snilay@cs.wisc.edu ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks 20210120Snilay@cs.wisc.edu ruby._cpu_ports = cpu_sequencers 20310012Snilay@cs.wisc.edu ruby.num_of_sequencers = len(cpu_sequencers) 20410525Snilay@cs.wisc.edu 20510630Snilay@cs.wisc.edu # Create a backing copy of physical memory in case required 20610630Snilay@cs.wisc.edu if options.access_backing_store: 20710706Spower.jg@gmail.com ruby.access_backing_store = True 20810706Spower.jg@gmail.com ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 20910630Snilay@cs.wisc.edu in_addr_map=False) 21010630Snilay@cs.wisc.edu 21110529Smorr@cs.wisc.edudef send_evicts(options): 21210529Smorr@cs.wisc.edu # currently, 2 scenarios warrant forwarding evictions to the CPU: 21310529Smorr@cs.wisc.edu # 1. The O3 model must keep the LSQ coherent with the caches 21410529Smorr@cs.wisc.edu # 2. The x86 mwait instruction is built on top of coherence invalidations 21510529Smorr@cs.wisc.edu if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 21610529Smorr@cs.wisc.edu return True 21710529Smorr@cs.wisc.edu return False 218