Ruby.py revision 10706
11689SN/A# Copyright (c) 2012 ARM Limited 29783Sandreas.hansson@arm.com# All rights reserved. 310239Sbinhpham@cs.rutgers.edu# 47598Sminkyu.jeong@arm.com# The license below extends only to copyright in the software and shall 57598Sminkyu.jeong@arm.com# not be construed as granting a license to any other intellectual 67598Sminkyu.jeong@arm.com# property including but not limited to intellectual property relating 77598Sminkyu.jeong@arm.com# to a hardware implementation of the functionality of the software 87598Sminkyu.jeong@arm.com# licensed hereunder. You may use the software subject to the license 97598Sminkyu.jeong@arm.com# terms below provided that you ensure that this notice is replicated 107598Sminkyu.jeong@arm.com# unmodified and in its entirety in all distributions of the software, 117598Sminkyu.jeong@arm.com# modified or unmodified, in source code or in binary form. 127598Sminkyu.jeong@arm.com# 137598Sminkyu.jeong@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 147598Sminkyu.jeong@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 152326SN/A# All rights reserved. 161689SN/A# 171689SN/A# Redistribution and use in source and binary forms, with or without 181689SN/A# modification, are permitted provided that the following conditions are 191689SN/A# met: redistributions of source code must retain the above copyright 201689SN/A# notice, this list of conditions and the following disclaimer; 211689SN/A# redistributions in binary form must reproduce the above copyright 221689SN/A# notice, this list of conditions and the following disclaimer in the 231689SN/A# documentation and/or other materials provided with the distribution; 241689SN/A# neither the name of the copyright holders nor the names of its 251689SN/A# contributors may be used to endorse or promote products derived from 261689SN/A# this software without specific prior written permission. 271689SN/A# 281689SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391689SN/A# 402665Ssaidi@eecs.umich.edu# Authors: Brad Beckmann 412665Ssaidi@eecs.umich.edu 421689SN/Aimport math 431689SN/Aimport m5 449944Smatt.horsnell@ARM.comfrom m5.objects import * 459944Smatt.horsnell@ARM.comfrom m5.defines import buildEnv 469944Smatt.horsnell@ARM.comfrom m5.util import addToPath, fatal 471060SN/A 481060SN/Aimport MemConfig 491689SN/AaddToPath('../topologies') 501060SN/A 511060SN/Adef define_options(parser): 521060SN/A # By default, ruby uses the simple timing cpu 538230Snate@binkert.org parser.set_defaults(cpu_type="timing") 546658Snate@binkert.org 558887Sgeoffrey.blake@arm.com parser.add_option("--ruby-clock", action="store", type="string", 562292SN/A default='2GHz', 571717SN/A help="Clock for blocks running at Ruby system's speed") 588229Snate@binkert.org 598232Snate@binkert.org parser.add_option("--access-backing-store", action="store_true", default=False, 609444SAndreas.Sandberg@ARM.com help="Should ruby maintain a second copy of memory") 618232Snate@binkert.org 629527SMatt.Horsnell@arm.com # Options related to cache structure 635529Snate@binkert.org parser.add_option("--ports", action="store", type="int", default=4, 641060SN/A help="used of transitions per cycle which is a proxy \ 656221Snate@binkert.org for the number of ports.") 666221Snate@binkert.org 671681SN/A # ruby network options 685529Snate@binkert.org parser.add_option("--topology", type="string", default="Crossbar", 692873Sktlim@umich.edu help="check src/mem/ruby/network/topologies for complete set") 704329Sktlim@umich.edu parser.add_option("--mesh-rows", type="int", default=1, 714329Sktlim@umich.edu help="the number of rows in the mesh topology") 724329Sktlim@umich.edu parser.add_option("--garnet-network", type="choice", 732292SN/A choices=['fixed', 'flexible'], help="'fixed'|'flexible'") 742292SN/A parser.add_option("--network-fault-model", action="store_true", default=False, 752292SN/A help="enable network fault model: see src/mem/ruby/network/fault_model/") 762292SN/A 772820Sktlim@umich.edu # ruby mapping options 782292SN/A parser.add_option("--numa-high-bit", type="int", default=0, 792820Sktlim@umich.edu help="high order address bit to use for numa mapping. " \ 809444SAndreas.Sandberg@ARM.com "0 = highest bit, not specified = lowest bit") 811060SN/A 8210172Sdam.sunwoo@arm.com parser.add_option("--recycle-latency", type="int", default=10, 8310172Sdam.sunwoo@arm.com help="Recycle latency for ruby controller input buffers") 8410172Sdam.sunwoo@arm.com 8510172Sdam.sunwoo@arm.com parser.add_option("--random_seed", type="int", default=1234, 8610172Sdam.sunwoo@arm.com help="Used for seeding the random number generator") 8710172Sdam.sunwoo@arm.com 8810172Sdam.sunwoo@arm.com protocol = buildEnv['PROTOCOL'] 8910172Sdam.sunwoo@arm.com exec "import %s" % protocol 9010172Sdam.sunwoo@arm.com eval("%s.define_options(parser)" % protocol) 9110172Sdam.sunwoo@arm.com 9210172Sdam.sunwoo@arm.comdef setup_memory_controllers(system, ruby, dir_cntrls, options): 9310172Sdam.sunwoo@arm.com ruby.block_size_bytes = options.cacheline_size 9410172Sdam.sunwoo@arm.com ruby.memory_size_bits = 48 952292SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 962292SN/A 972292SN/A if options.numa_high_bit: 981060SN/A numa_bit = options.numa_high_bit 991060SN/A else: 1001060SN/A # if the numa_bit is not specified, set the directory bits as the 1011060SN/A # lowest bits above the block offset bits, and the numa_bit as the 1021060SN/A # highest of those directory bits 1031060SN/A dir_bits = int(math.log(options.num_dirs, 2)) 1041681SN/A numa_bit = block_size_bits + dir_bits - 1 1056221Snate@binkert.org 1066221Snate@binkert.org index = 0 1076221Snate@binkert.org mem_ctrls = [] 1082292SN/A crossbars = [] 1092292SN/A 1102292SN/A # Sets bits to be used for interleaving. Creates memory controllers 1112292SN/A # attached to a directory controller. A separate controller is created 11210328Smitch.hayenga@arm.com # for each address range as the abstract memory can handle only one 1132292SN/A # contiguous address range as of now. 1142292SN/A for dir_cntrl in dir_cntrls: 1152292SN/A dir_cntrl.directory.numa_high_bit = numa_bit 1162292SN/A 1172292SN/A crossbar = None 1182292SN/A if len(system.mem_ranges) > 1: 1192292SN/A crossbar = NoncoherentXBar() 1201060SN/A crossbars.append(crossbar) 1211060SN/A dir_cntrl.memory = crossbar.slave 1221681SN/A 1231062SN/A for r in system.mem_ranges: 12410023Smatt.horsnell@ARM.com mem_ctrl = MemConfig.create_mem_ctrl( 12510023Smatt.horsnell@ARM.com MemConfig.get(options.mem_type), r, index, options.num_dirs, 12610023Smatt.horsnell@ARM.com int(math.log(options.num_dirs, 2)), options.cacheline_size) 12710023Smatt.horsnell@ARM.com 12811246Sradhika.jagtap@ARM.com mem_ctrls.append(mem_ctrl) 12911246Sradhika.jagtap@ARM.com 13011246Sradhika.jagtap@ARM.com if crossbar != None: 13111246Sradhika.jagtap@ARM.com mem_ctrl.port = crossbar.master 13211246Sradhika.jagtap@ARM.com else: 13311246Sradhika.jagtap@ARM.com mem_ctrl.port = dir_cntrl.memory 13411246Sradhika.jagtap@ARM.com 13511246Sradhika.jagtap@ARM.com index += 1 13611246Sradhika.jagtap@ARM.com 13711246Sradhika.jagtap@ARM.com system.mem_ctrls = mem_ctrls 13811246Sradhika.jagtap@ARM.com 13911246Sradhika.jagtap@ARM.com if len(crossbars) > 0: 14010023Smatt.horsnell@ARM.com ruby.crossbars = crossbars 14110023Smatt.horsnell@ARM.com 14210023Smatt.horsnell@ARM.com 14310023Smatt.horsnell@ARM.comdef create_topology(controllers, options): 1442292SN/A """ Called from create_system in configs/ruby/<protocol>.py 1451062SN/A Must return an object which is a subclass of BaseTopology 1462301SN/A found in configs/topologies/BaseTopology.py 1472301SN/A This is a wrapper for the legacy topologies. 1481062SN/A """ 1492727Sktlim@umich.edu exec "import %s as Topo" % options.topology 1501062SN/A topology = eval("Topo.%s(controllers)" % options.topology) 1511062SN/A return topology 1521062SN/A 1531062SN/Adef create_system(options, full_system, system, piobus = None, dma_ports = []): 1541062SN/A 1551062SN/A system.ruby = RubySystem() 1561062SN/A ruby = system.ruby 1571062SN/A 1581062SN/A # Set the network classes based on the command line options 1591062SN/A if options.garnet_network == "fixed": 1601062SN/A NetworkClass = GarnetNetwork_d 1611062SN/A IntLinkClass = GarnetIntLink_d 1621062SN/A ExtLinkClass = GarnetExtLink_d 1631062SN/A RouterClass = GarnetRouter_d 1641062SN/A InterfaceClass = GarnetNetworkInterface_d 1651062SN/A 1661062SN/A elif options.garnet_network == "flexible": 1671062SN/A NetworkClass = GarnetNetwork 1681062SN/A IntLinkClass = GarnetIntLink 1691062SN/A ExtLinkClass = GarnetExtLink 1701062SN/A RouterClass = GarnetRouter 1711062SN/A InterfaceClass = GarnetNetworkInterface 1721062SN/A 1731062SN/A else: 1741062SN/A NetworkClass = SimpleNetwork 1751062SN/A IntLinkClass = SimpleIntLink 1761062SN/A ExtLinkClass = SimpleExtLink 1771062SN/A RouterClass = Switch 1781062SN/A InterfaceClass = None 1791062SN/A 1801062SN/A # Instantiate the network object so that the controllers can connect to it. 1811062SN/A network = NetworkClass(ruby_system = ruby, topology = options.topology, 1821062SN/A routers = [], ext_links = [], int_links = [], netifs = []) 1831062SN/A ruby.network = network 1841062SN/A 1851062SN/A protocol = buildEnv['PROTOCOL'] 1861062SN/A exec "import %s" % protocol 1871062SN/A try: 1881062SN/A (cpu_sequencers, dir_cntrls, topology) = \ 1891062SN/A eval("%s.create_system(options, full_system, system, dma_ports,\ 1901062SN/A ruby)" 1912292SN/A % protocol) 1922292SN/A except: 1932292SN/A print "Error: could not create sytem for ruby protocol %s" % protocol 1942292SN/A raise 1951062SN/A 1961062SN/A # Create a port proxy for connecting the system port. This is 1971062SN/A # independent of the protocol and kept in the protocol-agnostic 1981062SN/A # part (i.e. here). 1991062SN/A sys_port_proxy = RubyPortProxy(ruby_system = ruby) 2001062SN/A 2011062SN/A # Give the system port proxy a SimObject parent without creating a 2022292SN/A # full-fledged controller 2032292SN/A system.sys_port_proxy = sys_port_proxy 2042292SN/A 2052292SN/A # Connect the system port for loading of binaries etc 2062292SN/A system.system_port = system.sys_port_proxy.slave 2072292SN/A 2082292SN/A # Create the network topology 2092292SN/A topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 2102292SN/A RouterClass) 2112292SN/A 2122301SN/A if InterfaceClass != None: 2132727Sktlim@umich.edu netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] 2142353SN/A network.netifs = netifs 2152727Sktlim@umich.edu 2162727Sktlim@umich.edu if options.network_fault_model: 2172727Sktlim@umich.edu assert(options.garnet_network == "fixed") 2186221Snate@binkert.org network.enable_fault_model = True 2192353SN/A network.fault_model = FaultModel() 2202727Sktlim@umich.edu 2212727Sktlim@umich.edu setup_memory_controllers(system, ruby, dir_cntrls, options) 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu # Connect the cpu sequencers and the piobus 2242353SN/A if piobus != None: 2252727Sktlim@umich.edu for cpu_seq in cpu_sequencers: 2262727Sktlim@umich.edu cpu_seq.pio_master_port = piobus.slave 2272727Sktlim@umich.edu cpu_seq.mem_master_port = piobus.slave 2286221Snate@binkert.org 2298240Snate@binkert.org if buildEnv['TARGET_ISA'] == "x86": 2302301SN/A cpu_seq.pio_slave_port = piobus.master 2312727Sktlim@umich.edu 2322301SN/A ruby._cpu_ports = cpu_sequencers 2332727Sktlim@umich.edu ruby.num_of_sequencers = len(cpu_sequencers) 2346221Snate@binkert.org ruby.random_seed = options.random_seed 2358240Snate@binkert.org 2362301SN/A # Create a backing copy of physical memory in case required 2372727Sktlim@umich.edu if options.access_backing_store: 2382301SN/A ruby.access_backing_store = True 2392727Sktlim@umich.edu ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0], 2406221Snate@binkert.org in_addr_map=False) 2418240Snate@binkert.org 2422301SN/Adef send_evicts(options): 2432727Sktlim@umich.edu # currently, 2 scenarios warrant forwarding evictions to the CPU: 2442301SN/A # 1. The O3 model must keep the LSQ coherent with the caches 2452727Sktlim@umich.edu # 2. The x86 mwait instruction is built on top of coherence invalidations 2466221Snate@binkert.org if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 2478240Snate@binkert.org return True 2482301SN/A return False 2492727Sktlim@umich.edu