Ruby.py revision 10551
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 136892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 146892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 156892SBrad.Beckmann@amd.com# All rights reserved. 166892SBrad.Beckmann@amd.com# 176892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 186892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 196892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 206892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 216892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 226892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 236892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 246892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 256892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 266892SBrad.Beckmann@amd.com# this software without specific prior written permission. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396892SBrad.Beckmann@amd.com# 406892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 416892SBrad.Beckmann@amd.com 427563SBrad.Beckmann@amd.comimport math 436892SBrad.Beckmann@amd.comimport m5 446892SBrad.Beckmann@amd.comfrom m5.objects import * 456892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 4610118Snilay@cs.wisc.edufrom m5.util import addToPath, fatal 4710118Snilay@cs.wisc.edu 4810524Snilay@cs.wisc.eduimport MemConfig 4910118Snilay@cs.wisc.eduaddToPath('../topologies') 506892SBrad.Beckmann@amd.com 517538SBrad.Beckmann@amd.comdef define_options(parser): 528939SBrad.Beckmann@amd.com # By default, ruby uses the simple timing cpu 538939SBrad.Beckmann@amd.com parser.set_defaults(cpu_type="timing") 548939SBrad.Beckmann@amd.com 559791Sakash.bagdia@arm.com parser.add_option("--ruby-clock", action="store", type="string", 569791Sakash.bagdia@arm.com default='2GHz', 579791Sakash.bagdia@arm.com help="Clock for blocks running at Ruby system's speed") 589791Sakash.bagdia@arm.com 5910525Snilay@cs.wisc.edu parser.add_option("--access-backing-store", action="store_true", default=False, 6010525Snilay@cs.wisc.edu help="Should ruby maintain a second copy of memory") 6110525Snilay@cs.wisc.edu 629841Snilay@cs.wisc.edu # Options related to cache structure 639841Snilay@cs.wisc.edu parser.add_option("--ports", action="store", type="int", default=4, 649841Snilay@cs.wisc.edu help="used of transitions per cycle which is a proxy \ 659841Snilay@cs.wisc.edu for the number of ports.") 669841Snilay@cs.wisc.edu 677538SBrad.Beckmann@amd.com # ruby network options 687538SBrad.Beckmann@amd.com parser.add_option("--topology", type="string", default="Crossbar", 697538SBrad.Beckmann@amd.com help="check src/mem/ruby/network/topologies for complete set") 707538SBrad.Beckmann@amd.com parser.add_option("--mesh-rows", type="int", default=1, 717538SBrad.Beckmann@amd.com help="the number of rows in the mesh topology") 729576Snilay@cs.wisc.edu parser.add_option("--garnet-network", type="choice", 739576Snilay@cs.wisc.edu choices=['fixed', 'flexible'], help="'fixed'|'flexible'") 748612Stushar@csail.mit.edu parser.add_option("--network-fault-model", action="store_true", default=False, 758612Stushar@csail.mit.edu help="enable network fault model: see src/mem/ruby/network/fault_model/") 767538SBrad.Beckmann@amd.com 777538SBrad.Beckmann@amd.com # ruby mapping options 787917SBrad.Beckmann@amd.com parser.add_option("--numa-high-bit", type="int", default=0, 797563SBrad.Beckmann@amd.com help="high order address bit to use for numa mapping. " \ 807563SBrad.Beckmann@amd.com "0 = highest bit, not specified = lowest bit") 817538SBrad.Beckmann@amd.com 827566SBrad.Beckmann@amd.com parser.add_option("--recycle-latency", type="int", default=10, 837566SBrad.Beckmann@amd.com help="Recycle latency for ruby controller input buffers") 847809Snilay@cs.wisc.edu 857809Snilay@cs.wisc.edu parser.add_option("--random_seed", type="int", default=1234, 867809Snilay@cs.wisc.edu help="Used for seeding the random number generator") 877809Snilay@cs.wisc.edu 887538SBrad.Beckmann@amd.com protocol = buildEnv['PROTOCOL'] 897538SBrad.Beckmann@amd.com exec "import %s" % protocol 907538SBrad.Beckmann@amd.com eval("%s.define_options(parser)" % protocol) 917538SBrad.Beckmann@amd.com 9210524Snilay@cs.wisc.edudef setup_memory_controllers(system, ruby, dir_cntrls, options): 9310524Snilay@cs.wisc.edu ruby.block_size_bytes = options.cacheline_size 9410524Snilay@cs.wisc.edu ruby.memory_size_bits = 48 9510524Snilay@cs.wisc.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 9610524Snilay@cs.wisc.edu 9710524Snilay@cs.wisc.edu if options.numa_high_bit: 9810524Snilay@cs.wisc.edu numa_bit = options.numa_high_bit 9910524Snilay@cs.wisc.edu else: 10010524Snilay@cs.wisc.edu # if the numa_bit is not specified, set the directory bits as the 10110524Snilay@cs.wisc.edu # lowest bits above the block offset bits, and the numa_bit as the 10210524Snilay@cs.wisc.edu # highest of those directory bits 10310524Snilay@cs.wisc.edu dir_bits = int(math.log(options.num_dirs, 2)) 10410524Snilay@cs.wisc.edu numa_bit = block_size_bits + dir_bits - 1 10510524Snilay@cs.wisc.edu 10610524Snilay@cs.wisc.edu index = 0 10710524Snilay@cs.wisc.edu mem_ctrls = [] 10810524Snilay@cs.wisc.edu crossbars = [] 10910524Snilay@cs.wisc.edu 11010524Snilay@cs.wisc.edu # Sets bits to be used for interleaving. Creates memory controllers 11110524Snilay@cs.wisc.edu # attached to a directory controller. A separate controller is created 11210524Snilay@cs.wisc.edu # for each address range as the abstract memory can handle only one 11310524Snilay@cs.wisc.edu # contiguous address range as of now. 11410524Snilay@cs.wisc.edu for dir_cntrl in dir_cntrls: 11510524Snilay@cs.wisc.edu dir_cntrl.directory.numa_high_bit = numa_bit 11610524Snilay@cs.wisc.edu 11710524Snilay@cs.wisc.edu crossbar = None 11810524Snilay@cs.wisc.edu if len(system.mem_ranges) > 1: 11910524Snilay@cs.wisc.edu crossbar = NoncoherentXBar() 12010524Snilay@cs.wisc.edu crossbars.append(crossbar) 12110524Snilay@cs.wisc.edu dir_cntrl.memory = crossbar.slave 12210524Snilay@cs.wisc.edu 12310524Snilay@cs.wisc.edu for r in system.mem_ranges: 12410524Snilay@cs.wisc.edu mem_ctrl = MemConfig.create_mem_ctrl( 12510524Snilay@cs.wisc.edu MemConfig.get(options.mem_type), r, index, options.num_dirs, 12610524Snilay@cs.wisc.edu int(math.log(options.num_dirs, 2)), options.cacheline_size) 12710524Snilay@cs.wisc.edu 12810524Snilay@cs.wisc.edu mem_ctrls.append(mem_ctrl) 12910524Snilay@cs.wisc.edu 13010524Snilay@cs.wisc.edu if crossbar != None: 13110524Snilay@cs.wisc.edu mem_ctrl.port = crossbar.master 13210524Snilay@cs.wisc.edu else: 13310524Snilay@cs.wisc.edu mem_ctrl.port = dir_cntrl.memory 13410524Snilay@cs.wisc.edu 13510524Snilay@cs.wisc.edu index += 1 13610524Snilay@cs.wisc.edu 13710524Snilay@cs.wisc.edu system.mem_ctrls = mem_ctrls 13810524Snilay@cs.wisc.edu 13910524Snilay@cs.wisc.edu if len(crossbars) > 0: 14010524Snilay@cs.wisc.edu ruby.crossbars = crossbars 14110524Snilay@cs.wisc.edu 14210524Snilay@cs.wisc.edu 1439100SBrad.Beckmann@amd.comdef create_topology(controllers, options): 1449100SBrad.Beckmann@amd.com """ Called from create_system in configs/ruby/<protocol>.py 1459100SBrad.Beckmann@amd.com Must return an object which is a subclass of BaseTopology 1469100SBrad.Beckmann@amd.com found in configs/topologies/BaseTopology.py 1479100SBrad.Beckmann@amd.com This is a wrapper for the legacy topologies. 1489100SBrad.Beckmann@amd.com """ 1499100SBrad.Beckmann@amd.com exec "import %s as Topo" % options.topology 1509100SBrad.Beckmann@amd.com topology = eval("Topo.%s(controllers)" % options.topology) 1519100SBrad.Beckmann@amd.com return topology 1529100SBrad.Beckmann@amd.com 15310519Snilay@cs.wisc.edudef create_system(options, full_system, system, piobus = None, dma_ports = []): 1546892SBrad.Beckmann@amd.com 15510524Snilay@cs.wisc.edu system.ruby = RubySystem() 1568436SBrad.Beckmann@amd.com ruby = system.ruby 1578436SBrad.Beckmann@amd.com 1588257SBrad.Beckmann@amd.com # Set the network classes based on the command line options 1598257SBrad.Beckmann@amd.com if options.garnet_network == "fixed": 16010122Snilay@cs.wisc.edu NetworkClass = GarnetNetwork_d 16110122Snilay@cs.wisc.edu IntLinkClass = GarnetIntLink_d 16210122Snilay@cs.wisc.edu ExtLinkClass = GarnetExtLink_d 16310122Snilay@cs.wisc.edu RouterClass = GarnetRouter_d 16410122Snilay@cs.wisc.edu InterfaceClass = GarnetNetworkInterface_d 16510122Snilay@cs.wisc.edu 1668257SBrad.Beckmann@amd.com elif options.garnet_network == "flexible": 16710122Snilay@cs.wisc.edu NetworkClass = GarnetNetwork 16810122Snilay@cs.wisc.edu IntLinkClass = GarnetIntLink 16910122Snilay@cs.wisc.edu ExtLinkClass = GarnetExtLink 17010122Snilay@cs.wisc.edu RouterClass = GarnetRouter 17110122Snilay@cs.wisc.edu InterfaceClass = GarnetNetworkInterface 17210122Snilay@cs.wisc.edu 1738257SBrad.Beckmann@amd.com else: 17410122Snilay@cs.wisc.edu NetworkClass = SimpleNetwork 17510122Snilay@cs.wisc.edu IntLinkClass = SimpleIntLink 17610122Snilay@cs.wisc.edu ExtLinkClass = SimpleExtLink 17710122Snilay@cs.wisc.edu RouterClass = Switch 17810122Snilay@cs.wisc.edu InterfaceClass = None 1799148Spowerjg@cs.wisc.edu 18010311Snilay@cs.wisc.edu # Instantiate the network object so that the controllers can connect to it. 18110311Snilay@cs.wisc.edu network = NetworkClass(ruby_system = ruby, topology = options.topology, 18210311Snilay@cs.wisc.edu routers = [], ext_links = [], int_links = [], netifs = []) 18310311Snilay@cs.wisc.edu ruby.network = network 18410311Snilay@cs.wisc.edu 18510551Ssteve.reinhardt@amd.com protocol = buildEnv['PROTOCOL'] 18610551Ssteve.reinhardt@amd.com exec "import %s" % protocol 18710311Snilay@cs.wisc.edu try: 18810311Snilay@cs.wisc.edu (cpu_sequencers, dir_cntrls, topology) = \ 18910551Ssteve.reinhardt@amd.com eval("%s.create_system(options, full_system, system, dma_ports,\ 19010551Ssteve.reinhardt@amd.com ruby)" 19110551Ssteve.reinhardt@amd.com % protocol) 19210311Snilay@cs.wisc.edu except: 19310551Ssteve.reinhardt@amd.com print "Error: could not create sytem for ruby protocol %s" % protocol 19410311Snilay@cs.wisc.edu raise 19510311Snilay@cs.wisc.edu 19610311Snilay@cs.wisc.edu # Create a port proxy for connecting the system port. This is 19710311Snilay@cs.wisc.edu # independent of the protocol and kept in the protocol-agnostic 19810311Snilay@cs.wisc.edu # part (i.e. here). 19910311Snilay@cs.wisc.edu sys_port_proxy = RubyPortProxy(ruby_system = ruby) 20010311Snilay@cs.wisc.edu 20110311Snilay@cs.wisc.edu # Give the system port proxy a SimObject parent without creating a 20210311Snilay@cs.wisc.edu # full-fledged controller 20310311Snilay@cs.wisc.edu system.sys_port_proxy = sys_port_proxy 20410311Snilay@cs.wisc.edu 20510311Snilay@cs.wisc.edu # Connect the system port for loading of binaries etc 20610311Snilay@cs.wisc.edu system.system_port = system.sys_port_proxy.slave 2079148Spowerjg@cs.wisc.edu 2089862Snilay@cs.wisc.edu # Create the network topology 2099862Snilay@cs.wisc.edu topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 21010122Snilay@cs.wisc.edu RouterClass) 21110122Snilay@cs.wisc.edu 21210122Snilay@cs.wisc.edu if InterfaceClass != None: 21310122Snilay@cs.wisc.edu netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] 21410122Snilay@cs.wisc.edu network.netifs = netifs 2158257SBrad.Beckmann@amd.com 2168612Stushar@csail.mit.edu if options.network_fault_model: 2178612Stushar@csail.mit.edu assert(options.garnet_network == "fixed") 2189593Snilay@cs.wisc.edu network.enable_fault_model = True 2199593Snilay@cs.wisc.edu network.fault_model = FaultModel() 2206892SBrad.Beckmann@amd.com 22110524Snilay@cs.wisc.edu setup_memory_controllers(system, ruby, dir_cntrls, options) 22210116Snilay@cs.wisc.edu 22310116Snilay@cs.wisc.edu # Connect the cpu sequencers and the piobus 22410116Snilay@cs.wisc.edu if piobus != None: 22510116Snilay@cs.wisc.edu for cpu_seq in cpu_sequencers: 22610116Snilay@cs.wisc.edu cpu_seq.pio_master_port = piobus.slave 22710116Snilay@cs.wisc.edu cpu_seq.mem_master_port = piobus.slave 22810116Snilay@cs.wisc.edu 22910116Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 23010116Snilay@cs.wisc.edu cpu_seq.pio_slave_port = piobus.master 23110116Snilay@cs.wisc.edu 23210120Snilay@cs.wisc.edu ruby._cpu_ports = cpu_sequencers 23310012Snilay@cs.wisc.edu ruby.num_of_sequencers = len(cpu_sequencers) 2347809Snilay@cs.wisc.edu ruby.random_seed = options.random_seed 23510525Snilay@cs.wisc.edu 23610529Smorr@cs.wisc.edudef send_evicts(options): 23710529Smorr@cs.wisc.edu # currently, 2 scenarios warrant forwarding evictions to the CPU: 23810529Smorr@cs.wisc.edu # 1. The O3 model must keep the LSQ coherent with the caches 23910529Smorr@cs.wisc.edu # 2. The x86 mwait instruction is built on top of coherence invalidations 24010529Smorr@cs.wisc.edu if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 24110529Smorr@cs.wisc.edu return True 24210529Smorr@cs.wisc.edu return False 24310529Smorr@cs.wisc.edu 24410525Snilay@cs.wisc.edu # Create a backing copy of physical memory in case required 24510525Snilay@cs.wisc.edu if options.access_backing_store: 24610525Snilay@cs.wisc.edu ruby.phys_mem = SimpleMemory(range=AddrRange(options.mem_size), 24710525Snilay@cs.wisc.edu in_addr_map=False) 248