Ruby.py revision 10525
11689SN/A# Copyright (c) 2012 ARM Limited 210333Smitch.hayenga@arm.com# All rights reserved. 39920Syasuko.eckert@amd.com# 47944SGiacomo.Gabrielli@arm.com# The license below extends only to copyright in the software and shall 57944SGiacomo.Gabrielli@arm.com# not be construed as granting a license to any other intellectual 67944SGiacomo.Gabrielli@arm.com# property including but not limited to intellectual property relating 77944SGiacomo.Gabrielli@arm.com# to a hardware implementation of the functionality of the software 87944SGiacomo.Gabrielli@arm.com# licensed hereunder. You may use the software subject to the license 97944SGiacomo.Gabrielli@arm.com# terms below provided that you ensure that this notice is replicated 107944SGiacomo.Gabrielli@arm.com# unmodified and in its entirety in all distributions of the software, 117944SGiacomo.Gabrielli@arm.com# modified or unmodified, in source code or in binary form. 127944SGiacomo.Gabrielli@arm.com# 137944SGiacomo.Gabrielli@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 147944SGiacomo.Gabrielli@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 152326SN/A# All rights reserved. 161689SN/A# 171689SN/A# Redistribution and use in source and binary forms, with or without 181689SN/A# modification, are permitted provided that the following conditions are 191689SN/A# met: redistributions of source code must retain the above copyright 201689SN/A# notice, this list of conditions and the following disclaimer; 211689SN/A# redistributions in binary form must reproduce the above copyright 221689SN/A# notice, this list of conditions and the following disclaimer in the 231689SN/A# documentation and/or other materials provided with the distribution; 241689SN/A# neither the name of the copyright holders nor the names of its 251689SN/A# contributors may be used to endorse or promote products derived from 261689SN/A# this software without specific prior written permission. 271689SN/A# 281689SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391689SN/A# 402665Ssaidi@eecs.umich.edu# Authors: Brad Beckmann 412665Ssaidi@eecs.umich.edu 422831Sksewell@umich.eduimport math 431689SN/Aimport m5 441689SN/Afrom m5.objects import * 459944Smatt.horsnell@ARM.comfrom m5.defines import buildEnv 469944Smatt.horsnell@ARM.comfrom m5.util import addToPath, fatal 479944Smatt.horsnell@ARM.com 482064SN/Aimport MemConfig 491060SN/AaddToPath('../topologies') 501060SN/A 512292SN/Adef define_options(parser): 521717SN/A # By default, ruby uses the simple timing cpu 538232Snate@binkert.org parser.set_defaults(cpu_type="timing") 544762Snate@binkert.org 556221Snate@binkert.org parser.add_option("--ruby-clock", action="store", type="string", 564762Snate@binkert.org default='2GHz', 571060SN/A help="Clock for blocks running at Ruby system's speed") 588737Skoansin.tan@gmail.com 598737Skoansin.tan@gmail.com parser.add_option("--access-backing-store", action="store_true", default=False, 608737Skoansin.tan@gmail.com help="Should ruby maintain a second copy of memory") 615529Snate@binkert.org 621061SN/A # Options related to cache structure 632292SN/A parser.add_option("--ports", action="store", type="int", default=4, 645606Snate@binkert.org help="used of transitions per cycle which is a proxy \ 658581Ssteve.reinhardt@amd.com for the number of ports.") 668581Ssteve.reinhardt@amd.com 671060SN/A # ruby network options 682292SN/A parser.add_option("--topology", type="string", default="Crossbar", 692292SN/A help="check src/mem/ruby/network/topologies for complete set") 702292SN/A parser.add_option("--mesh-rows", type="int", default=1, 712292SN/A help="the number of rows in the mesh topology") 722292SN/A parser.add_option("--garnet-network", type="choice", 732292SN/A choices=['fixed', 'flexible'], help="'fixed'|'flexible'") 742326SN/A parser.add_option("--network-fault-model", action="store_true", default=False, 752292SN/A help="enable network fault model: see src/mem/ruby/network/fault_model/") 762292SN/A 772292SN/A # ruby mapping options 782292SN/A parser.add_option("--numa-high-bit", type="int", default=0, 792292SN/A help="high order address bit to use for numa mapping. " \ 802292SN/A "0 = highest bit, not specified = lowest bit") 815336Shines@cs.fsu.edu 822292SN/A parser.add_option("--recycle-latency", type="int", default=10, 834873Sstever@eecs.umich.edu help="Recycle latency for ruby controller input buffers") 842292SN/A 852292SN/A parser.add_option("--random_seed", type="int", default=1234, 862292SN/A help="Used for seeding the random number generator") 874329Sktlim@umich.edu 885529Snate@binkert.org protocol = buildEnv['PROTOCOL'] 894329Sktlim@umich.edu exec "import %s" % protocol 904329Sktlim@umich.edu eval("%s.define_options(parser)" % protocol) 914329Sktlim@umich.edu 922292SN/Adef setup_memory_controllers(system, ruby, dir_cntrls, options): 932292SN/A ruby.block_size_bytes = options.cacheline_size 942292SN/A ruby.memory_size_bits = 48 952292SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 962292SN/A 972292SN/A if options.numa_high_bit: 985529Snate@binkert.org numa_bit = options.numa_high_bit 991060SN/A else: 1009920Syasuko.eckert@amd.com # if the numa_bit is not specified, set the directory bits as the 1019920Syasuko.eckert@amd.com # lowest bits above the block offset bits, and the numa_bit as the 1029920Syasuko.eckert@amd.com # highest of those directory bits 1031060SN/A dir_bits = int(math.log(options.num_dirs, 2)) 1041060SN/A numa_bit = block_size_bits + dir_bits - 1 1051060SN/A 1062326SN/A index = 0 1071060SN/A mem_ctrls = [] 1081060SN/A crossbars = [] 1091060SN/A 1101060SN/A # Sets bits to be used for interleaving. Creates memory controllers 1112292SN/A # attached to a directory controller. A separate controller is created 1126221Snate@binkert.org # for each address range as the abstract memory can handle only one 1136221Snate@binkert.org # contiguous address range as of now. 1146221Snate@binkert.org for dir_cntrl in dir_cntrls: 1151060SN/A dir_cntrl.directory.numa_high_bit = numa_bit 1161060SN/A 1172307SN/A crossbar = None 1182292SN/A if len(system.mem_ranges) > 1: 1192980Sgblack@eecs.umich.edu crossbar = NoncoherentXBar() 1202292SN/A crossbars.append(crossbar) 1212292SN/A dir_cntrl.memory = crossbar.slave 1222292SN/A 1232292SN/A for r in system.mem_ranges: 1242292SN/A mem_ctrl = MemConfig.create_mem_ctrl( 1252292SN/A MemConfig.get(options.mem_type), r, index, options.num_dirs, 1262292SN/A int(math.log(options.num_dirs, 2)), options.cacheline_size) 1272292SN/A 1282292SN/A mem_ctrls.append(mem_ctrl) 1292292SN/A 1306221Snate@binkert.org if crossbar != None: 1316221Snate@binkert.org mem_ctrl.port = crossbar.master 1322292SN/A else: 1332292SN/A mem_ctrl.port = dir_cntrl.memory 1342292SN/A 1352292SN/A index += 1 1362292SN/A 1372292SN/A system.mem_ctrls = mem_ctrls 1382292SN/A 1392292SN/A if len(crossbars) > 0: 1402292SN/A ruby.crossbars = crossbars 1416221Snate@binkert.org 1426221Snate@binkert.org 1432292SN/Adef create_topology(controllers, options): 1442292SN/A """ Called from create_system in configs/ruby/<protocol>.py 1452831Sksewell@umich.edu Must return an object which is a subclass of BaseTopology 1462292SN/A found in configs/topologies/BaseTopology.py 1472292SN/A This is a wrapper for the legacy topologies. 1482292SN/A """ 1492292SN/A exec "import %s as Topo" % options.topology 1502292SN/A topology = eval("Topo.%s(controllers)" % options.topology) 1512292SN/A return topology 1522292SN/A 1532292SN/Adef create_system(options, full_system, system, piobus = None, dma_ports = []): 1542292SN/A 1556221Snate@binkert.org system.ruby = RubySystem() 1566221Snate@binkert.org ruby = system.ruby 1572292SN/A 1582292SN/A # Set the network classes based on the command line options 1592831Sksewell@umich.edu if options.garnet_network == "fixed": 1602292SN/A NetworkClass = GarnetNetwork_d 1612292SN/A IntLinkClass = GarnetIntLink_d 1622292SN/A ExtLinkClass = GarnetExtLink_d 1632292SN/A RouterClass = GarnetRouter_d 1642292SN/A InterfaceClass = GarnetNetworkInterface_d 1652292SN/A 1662292SN/A elif options.garnet_network == "flexible": 1672292SN/A NetworkClass = GarnetNetwork 1682292SN/A IntLinkClass = GarnetIntLink 1692292SN/A ExtLinkClass = GarnetExtLink 1702326SN/A RouterClass = GarnetRouter 1712348SN/A InterfaceClass = GarnetNetworkInterface 1722326SN/A 1732326SN/A else: 1742348SN/A NetworkClass = SimpleNetwork 1752292SN/A IntLinkClass = SimpleIntLink 1762292SN/A ExtLinkClass = SimpleExtLink 1772292SN/A RouterClass = Switch 1782292SN/A InterfaceClass = None 1792292SN/A 1802292SN/A # Instantiate the network object so that the controllers can connect to it. 1812292SN/A network = NetworkClass(ruby_system = ruby, topology = options.topology, 1821060SN/A routers = [], ext_links = [], int_links = [], netifs = []) 1831060SN/A ruby.network = network 1841061SN/A 1851060SN/A protocol = buildEnv['PROTOCOL'] 1861062SN/A exec "import %s" % protocol 1871062SN/A try: 1882301SN/A (cpu_sequencers, dir_cntrls, topology) = \ 1891062SN/A eval("%s.create_system(options, full_system, system, dma_ports,\ 1901062SN/A ruby)" 1911062SN/A % protocol) 1921062SN/A except: 1931062SN/A print "Error: could not create sytem for ruby protocol %s" % protocol 1941062SN/A raise 1951062SN/A 1961062SN/A # Create a port proxy for connecting the system port. This is 1971062SN/A # independent of the protocol and kept in the protocol-agnostic 1981062SN/A # part (i.e. here). 1992301SN/A sys_port_proxy = RubyPortProxy(ruby_system = ruby) 2002301SN/A 2012301SN/A # Give the system port proxy a SimObject parent without creating a 2022301SN/A # full-fledged controller 2031062SN/A system.sys_port_proxy = sys_port_proxy 2041062SN/A 2051062SN/A # Connect the system port for loading of binaries etc 2061062SN/A system.system_port = system.sys_port_proxy.slave 2071062SN/A 2081062SN/A # Create the network topology 2091062SN/A topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 2101062SN/A RouterClass) 2111062SN/A 2121062SN/A if InterfaceClass != None: 2131062SN/A netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] 2141062SN/A network.netifs = netifs 2151062SN/A 2161062SN/A if options.network_fault_model: 2171062SN/A assert(options.garnet_network == "fixed") 2181062SN/A network.enable_fault_model = True 2191062SN/A network.fault_model = FaultModel() 2201062SN/A 2211062SN/A setup_memory_controllers(system, ruby, dir_cntrls, options) 2221062SN/A 2231062SN/A # Connect the cpu sequencers and the piobus 2241062SN/A if piobus != None: 2251062SN/A for cpu_seq in cpu_sequencers: 2261062SN/A cpu_seq.pio_master_port = piobus.slave 2271062SN/A cpu_seq.mem_master_port = piobus.slave 2281062SN/A 2291062SN/A if buildEnv['TARGET_ISA'] == "x86": 2301062SN/A cpu_seq.pio_slave_port = piobus.master 2311062SN/A 2321062SN/A ruby._cpu_ports = cpu_sequencers 2331062SN/A ruby.num_of_sequencers = len(cpu_sequencers) 2341062SN/A ruby.random_seed = options.random_seed 2351062SN/A 2361062SN/A # Create a backing copy of physical memory in case required 2371062SN/A if options.access_backing_store: 2381062SN/A ruby.phys_mem = SimpleMemory(range=AddrRange(options.mem_size), 2391062SN/A in_addr_map=False) 2401062SN/A