Ruby.py revision 10120
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 136892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 146892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 156892SBrad.Beckmann@amd.com# All rights reserved. 166892SBrad.Beckmann@amd.com# 176892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 186892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 196892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 206892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 216892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 226892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 236892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 246892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 256892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 266892SBrad.Beckmann@amd.com# this software without specific prior written permission. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396892SBrad.Beckmann@amd.com# 406892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 416892SBrad.Beckmann@amd.com 427563SBrad.Beckmann@amd.comimport math 436892SBrad.Beckmann@amd.comimport m5 446892SBrad.Beckmann@amd.comfrom m5.objects import * 456892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 4610118Snilay@cs.wisc.edufrom m5.util import addToPath, fatal 4710118Snilay@cs.wisc.edu 4810118Snilay@cs.wisc.eduaddToPath('../topologies') 496892SBrad.Beckmann@amd.com 507538SBrad.Beckmann@amd.comdef define_options(parser): 518939SBrad.Beckmann@amd.com # By default, ruby uses the simple timing cpu 528939SBrad.Beckmann@amd.com parser.set_defaults(cpu_type="timing") 538939SBrad.Beckmann@amd.com 549791Sakash.bagdia@arm.com parser.add_option("--ruby-clock", action="store", type="string", 559791Sakash.bagdia@arm.com default='2GHz', 569791Sakash.bagdia@arm.com help="Clock for blocks running at Ruby system's speed") 579791Sakash.bagdia@arm.com 589841Snilay@cs.wisc.edu # Options related to cache structure 599841Snilay@cs.wisc.edu parser.add_option("--ports", action="store", type="int", default=4, 609841Snilay@cs.wisc.edu help="used of transitions per cycle which is a proxy \ 619841Snilay@cs.wisc.edu for the number of ports.") 629841Snilay@cs.wisc.edu 637538SBrad.Beckmann@amd.com # ruby network options 647538SBrad.Beckmann@amd.com parser.add_option("--topology", type="string", default="Crossbar", 657538SBrad.Beckmann@amd.com help="check src/mem/ruby/network/topologies for complete set") 667538SBrad.Beckmann@amd.com parser.add_option("--mesh-rows", type="int", default=1, 677538SBrad.Beckmann@amd.com help="the number of rows in the mesh topology") 689576Snilay@cs.wisc.edu parser.add_option("--garnet-network", type="choice", 699576Snilay@cs.wisc.edu choices=['fixed', 'flexible'], help="'fixed'|'flexible'") 708612Stushar@csail.mit.edu parser.add_option("--network-fault-model", action="store_true", default=False, 718612Stushar@csail.mit.edu help="enable network fault model: see src/mem/ruby/network/fault_model/") 727538SBrad.Beckmann@amd.com 737538SBrad.Beckmann@amd.com # ruby mapping options 747917SBrad.Beckmann@amd.com parser.add_option("--numa-high-bit", type="int", default=0, 757563SBrad.Beckmann@amd.com help="high order address bit to use for numa mapping. " \ 767563SBrad.Beckmann@amd.com "0 = highest bit, not specified = lowest bit") 777538SBrad.Beckmann@amd.com 787538SBrad.Beckmann@amd.com # ruby sparse memory options 797538SBrad.Beckmann@amd.com parser.add_option("--use-map", action="store_true", default=False) 807538SBrad.Beckmann@amd.com parser.add_option("--map-levels", type="int", default=4) 817538SBrad.Beckmann@amd.com 827566SBrad.Beckmann@amd.com parser.add_option("--recycle-latency", type="int", default=10, 837566SBrad.Beckmann@amd.com help="Recycle latency for ruby controller input buffers") 847809Snilay@cs.wisc.edu 857809Snilay@cs.wisc.edu parser.add_option("--random_seed", type="int", default=1234, 867809Snilay@cs.wisc.edu help="Used for seeding the random number generator") 877809Snilay@cs.wisc.edu 888638Sgloh parser.add_option("--ruby_stats", type="string", default="ruby.stats") 898638Sgloh 907538SBrad.Beckmann@amd.com protocol = buildEnv['PROTOCOL'] 917538SBrad.Beckmann@amd.com exec "import %s" % protocol 927538SBrad.Beckmann@amd.com eval("%s.define_options(parser)" % protocol) 937538SBrad.Beckmann@amd.com 949100SBrad.Beckmann@amd.comdef create_topology(controllers, options): 959100SBrad.Beckmann@amd.com """ Called from create_system in configs/ruby/<protocol>.py 969100SBrad.Beckmann@amd.com Must return an object which is a subclass of BaseTopology 979100SBrad.Beckmann@amd.com found in configs/topologies/BaseTopology.py 989100SBrad.Beckmann@amd.com This is a wrapper for the legacy topologies. 999100SBrad.Beckmann@amd.com """ 1009100SBrad.Beckmann@amd.com exec "import %s as Topo" % options.topology 1019100SBrad.Beckmann@amd.com topology = eval("Topo.%s(controllers)" % options.topology) 1029100SBrad.Beckmann@amd.com return topology 1039100SBrad.Beckmann@amd.com 1048929Snilay@cs.wisc.edudef create_system(options, system, piobus = None, dma_ports = []): 1056892SBrad.Beckmann@amd.com 10610012Snilay@cs.wisc.edu system.ruby = RubySystem(no_mem_vec = options.use_map) 1078436SBrad.Beckmann@amd.com ruby = system.ruby 1088436SBrad.Beckmann@amd.com 1097032SBrad.Beckmann@amd.com protocol = buildEnv['PROTOCOL'] 1107032SBrad.Beckmann@amd.com exec "import %s" % protocol 1116923SBrad.Beckmann@amd.com try: 1129100SBrad.Beckmann@amd.com (cpu_sequencers, dir_cntrls, topology) = \ 11310116Snilay@cs.wisc.edu eval("%s.create_system(options, system, dma_ports, ruby)" 1147557SBrad.Beckmann@amd.com % protocol) 1156923SBrad.Beckmann@amd.com except: 1166923SBrad.Beckmann@amd.com print "Error: could not create sytem for ruby protocol %s" % protocol 1177557SBrad.Beckmann@amd.com raise 1188257SBrad.Beckmann@amd.com 1198706Sandreas.hansson@arm.com # Create a port proxy for connecting the system port. This is 1208706Sandreas.hansson@arm.com # independent of the protocol and kept in the protocol-agnostic 1218706Sandreas.hansson@arm.com # part (i.e. here). 1228923Sandreas.hansson@arm.com sys_port_proxy = RubyPortProxy(ruby_system = ruby) 1238706Sandreas.hansson@arm.com # Give the system port proxy a SimObject parent without creating a 1248706Sandreas.hansson@arm.com # full-fledged controller 1258706Sandreas.hansson@arm.com system.sys_port_proxy = sys_port_proxy 1268706Sandreas.hansson@arm.com 1278732Sandreas.hansson@arm.com # Connect the system port for loading of binaries etc 1288839Sandreas.hansson@arm.com system.system_port = system.sys_port_proxy.slave 1298732Sandreas.hansson@arm.com 1308732Sandreas.hansson@arm.com 1318257SBrad.Beckmann@amd.com # 1328257SBrad.Beckmann@amd.com # Set the network classes based on the command line options 1338257SBrad.Beckmann@amd.com # 1348257SBrad.Beckmann@amd.com if options.garnet_network == "fixed": 1358257SBrad.Beckmann@amd.com class NetworkClass(GarnetNetwork_d): pass 1368257SBrad.Beckmann@amd.com class IntLinkClass(GarnetIntLink_d): pass 1378257SBrad.Beckmann@amd.com class ExtLinkClass(GarnetExtLink_d): pass 1388257SBrad.Beckmann@amd.com class RouterClass(GarnetRouter_d): pass 1398257SBrad.Beckmann@amd.com elif options.garnet_network == "flexible": 1408257SBrad.Beckmann@amd.com class NetworkClass(GarnetNetwork): pass 1418257SBrad.Beckmann@amd.com class IntLinkClass(GarnetIntLink): pass 1428257SBrad.Beckmann@amd.com class ExtLinkClass(GarnetExtLink): pass 1438257SBrad.Beckmann@amd.com class RouterClass(GarnetRouter): pass 1448257SBrad.Beckmann@amd.com else: 1458257SBrad.Beckmann@amd.com class NetworkClass(SimpleNetwork): pass 1468258SBrad.Beckmann@amd.com class IntLinkClass(SimpleIntLink): pass 1478258SBrad.Beckmann@amd.com class ExtLinkClass(SimpleExtLink): pass 1489274Snilay@cs.wisc.edu class RouterClass(Switch): pass 1499148Spowerjg@cs.wisc.edu 1509148Spowerjg@cs.wisc.edu 1519862Snilay@cs.wisc.edu # Create the network topology 1529862Snilay@cs.wisc.edu network = NetworkClass(ruby_system = ruby, topology = topology.description, 1539862Snilay@cs.wisc.edu routers = [], ext_links = [], int_links = []) 1549862Snilay@cs.wisc.edu topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 1559862Snilay@cs.wisc.edu RouterClass) 1568257SBrad.Beckmann@amd.com 1578612Stushar@csail.mit.edu if options.network_fault_model: 1588612Stushar@csail.mit.edu assert(options.garnet_network == "fixed") 1599593Snilay@cs.wisc.edu network.enable_fault_model = True 1609593Snilay@cs.wisc.edu network.fault_model = FaultModel() 1616892SBrad.Beckmann@amd.com 1626903SBrad.Beckmann@amd.com # 1637563SBrad.Beckmann@amd.com # Loop through the directory controlers. 1647025SBrad.Beckmann@amd.com # Determine the total memory size of the ruby system and verify it is equal 1659148Spowerjg@cs.wisc.edu # to physmem. However, if Ruby memory is using sparse memory in SE 1667025SBrad.Beckmann@amd.com # mode, then the system should not back-up the memory state with 1677025SBrad.Beckmann@amd.com # the Memory Vector and thus the memory size bytes should stay at 0. 1687563SBrad.Beckmann@amd.com # Also set the numa bits to the appropriate values. 1696903SBrad.Beckmann@amd.com # 1706903SBrad.Beckmann@amd.com total_mem_size = MemorySize('0B') 1717563SBrad.Beckmann@amd.com 1729318Spower.jg@gmail.com ruby.block_size_bytes = options.cacheline_size 1739318Spower.jg@gmail.com block_size_bits = int(math.log(options.cacheline_size, 2)) 1747563SBrad.Beckmann@amd.com 1757563SBrad.Beckmann@amd.com if options.numa_high_bit: 1767563SBrad.Beckmann@amd.com numa_bit = options.numa_high_bit 1777563SBrad.Beckmann@amd.com else: 1789318Spower.jg@gmail.com # if the numa_bit is not specified, set the directory bits as the 1799318Spower.jg@gmail.com # lowest bits above the block offset bits, and the numa_bit as the 1809318Spower.jg@gmail.com # highest of those directory bits 18110004Snilay@cs.wisc.edu dir_bits = int(math.log(options.num_dirs, 2)) 1829318Spower.jg@gmail.com numa_bit = block_size_bits + dir_bits - 1 1839148Spowerjg@cs.wisc.edu 1846903SBrad.Beckmann@amd.com for dir_cntrl in dir_cntrls: 1856903SBrad.Beckmann@amd.com total_mem_size.value += dir_cntrl.directory.size.value 1867563SBrad.Beckmann@amd.com dir_cntrl.directory.numa_high_bit = numa_bit 1879148Spowerjg@cs.wisc.edu 1889826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1898931Sandreas.hansson@arm.com assert(total_mem_size.value == phys_mem_size) 1906892SBrad.Beckmann@amd.com 1918436SBrad.Beckmann@amd.com ruby.network = network 1928436SBrad.Beckmann@amd.com ruby.mem_size = total_mem_size 19310116Snilay@cs.wisc.edu 19410116Snilay@cs.wisc.edu # Connect the cpu sequencers and the piobus 19510116Snilay@cs.wisc.edu if piobus != None: 19610116Snilay@cs.wisc.edu for cpu_seq in cpu_sequencers: 19710116Snilay@cs.wisc.edu cpu_seq.pio_master_port = piobus.slave 19810116Snilay@cs.wisc.edu cpu_seq.mem_master_port = piobus.slave 19910116Snilay@cs.wisc.edu 20010116Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 20110116Snilay@cs.wisc.edu cpu_seq.pio_slave_port = piobus.master 20210116Snilay@cs.wisc.edu 20310120Snilay@cs.wisc.edu ruby._cpu_ports = cpu_sequencers 20410012Snilay@cs.wisc.edu ruby.num_of_sequencers = len(cpu_sequencers) 2057809Snilay@cs.wisc.edu ruby.random_seed = options.random_seed 206