Ruby.py revision 10116
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited
28706Sandreas.hansson@arm.com# All rights reserved.
38706Sandreas.hansson@arm.com#
48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
88706Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form.
128706Sandreas.hansson@arm.com#
136892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
146892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
156892SBrad.Beckmann@amd.com# All rights reserved.
166892SBrad.Beckmann@amd.com#
176892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without
186892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are
196892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright
206892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer;
216892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright
226892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the
236892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution;
246892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its
256892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from
266892SBrad.Beckmann@amd.com# this software without specific prior written permission.
276892SBrad.Beckmann@amd.com#
286892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
296892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
306892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
316892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
326892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
336892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
346892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
356892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
366892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
376892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
386892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
396892SBrad.Beckmann@amd.com#
406892SBrad.Beckmann@amd.com# Authors: Brad Beckmann
416892SBrad.Beckmann@amd.com
427563SBrad.Beckmann@amd.comimport math
436892SBrad.Beckmann@amd.comimport m5
446892SBrad.Beckmann@amd.comfrom m5.objects import *
456892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv
466892SBrad.Beckmann@amd.com
477538SBrad.Beckmann@amd.comdef define_options(parser):
488939SBrad.Beckmann@amd.com    # By default, ruby uses the simple timing cpu
498939SBrad.Beckmann@amd.com    parser.set_defaults(cpu_type="timing")
508939SBrad.Beckmann@amd.com
519791Sakash.bagdia@arm.com    parser.add_option("--ruby-clock", action="store", type="string",
529791Sakash.bagdia@arm.com                      default='2GHz',
539791Sakash.bagdia@arm.com                      help="Clock for blocks running at Ruby system's speed")
549791Sakash.bagdia@arm.com
559841Snilay@cs.wisc.edu    # Options related to cache structure
569841Snilay@cs.wisc.edu    parser.add_option("--ports", action="store", type="int", default=4,
579841Snilay@cs.wisc.edu                      help="used of transitions per cycle which is a proxy \
589841Snilay@cs.wisc.edu                            for the number of ports.")
599841Snilay@cs.wisc.edu
607538SBrad.Beckmann@amd.com    # ruby network options
617538SBrad.Beckmann@amd.com    parser.add_option("--topology", type="string", default="Crossbar",
627538SBrad.Beckmann@amd.com                 help="check src/mem/ruby/network/topologies for complete set")
637538SBrad.Beckmann@amd.com    parser.add_option("--mesh-rows", type="int", default=1,
647538SBrad.Beckmann@amd.com                      help="the number of rows in the mesh topology")
659576Snilay@cs.wisc.edu    parser.add_option("--garnet-network", type="choice",
669576Snilay@cs.wisc.edu                      choices=['fixed', 'flexible'], help="'fixed'|'flexible'")
678612Stushar@csail.mit.edu    parser.add_option("--network-fault-model", action="store_true", default=False,
688612Stushar@csail.mit.edu                      help="enable network fault model: see src/mem/ruby/network/fault_model/")
697538SBrad.Beckmann@amd.com
707538SBrad.Beckmann@amd.com    # ruby mapping options
717917SBrad.Beckmann@amd.com    parser.add_option("--numa-high-bit", type="int", default=0,
727563SBrad.Beckmann@amd.com                      help="high order address bit to use for numa mapping. " \
737563SBrad.Beckmann@amd.com                           "0 = highest bit, not specified = lowest bit")
747538SBrad.Beckmann@amd.com
757538SBrad.Beckmann@amd.com    # ruby sparse memory options
767538SBrad.Beckmann@amd.com    parser.add_option("--use-map", action="store_true", default=False)
777538SBrad.Beckmann@amd.com    parser.add_option("--map-levels", type="int", default=4)
787538SBrad.Beckmann@amd.com
797566SBrad.Beckmann@amd.com    parser.add_option("--recycle-latency", type="int", default=10,
807566SBrad.Beckmann@amd.com                      help="Recycle latency for ruby controller input buffers")
817809Snilay@cs.wisc.edu
827809Snilay@cs.wisc.edu    parser.add_option("--random_seed", type="int", default=1234,
837809Snilay@cs.wisc.edu                      help="Used for seeding the random number generator")
847809Snilay@cs.wisc.edu
858638Sgloh    parser.add_option("--ruby_stats", type="string", default="ruby.stats")
868638Sgloh
877538SBrad.Beckmann@amd.com    protocol = buildEnv['PROTOCOL']
887538SBrad.Beckmann@amd.com    exec "import %s" % protocol
897538SBrad.Beckmann@amd.com    eval("%s.define_options(parser)" % protocol)
907538SBrad.Beckmann@amd.com
919100SBrad.Beckmann@amd.comdef create_topology(controllers, options):
929100SBrad.Beckmann@amd.com    """ Called from create_system in configs/ruby/<protocol>.py
939100SBrad.Beckmann@amd.com        Must return an object which is a subclass of BaseTopology
949100SBrad.Beckmann@amd.com        found in configs/topologies/BaseTopology.py
959100SBrad.Beckmann@amd.com        This is a wrapper for the legacy topologies.
969100SBrad.Beckmann@amd.com    """
979100SBrad.Beckmann@amd.com    exec "import %s as Topo" % options.topology
989100SBrad.Beckmann@amd.com    topology = eval("Topo.%s(controllers)" % options.topology)
999100SBrad.Beckmann@amd.com    return topology
1009100SBrad.Beckmann@amd.com
1018929Snilay@cs.wisc.edudef create_system(options, system, piobus = None, dma_ports = []):
1026892SBrad.Beckmann@amd.com
10310012Snilay@cs.wisc.edu    system.ruby = RubySystem(no_mem_vec = options.use_map)
1048436SBrad.Beckmann@amd.com    ruby = system.ruby
1058436SBrad.Beckmann@amd.com
1067032SBrad.Beckmann@amd.com    protocol = buildEnv['PROTOCOL']
1077032SBrad.Beckmann@amd.com    exec "import %s" % protocol
1086923SBrad.Beckmann@amd.com    try:
1099100SBrad.Beckmann@amd.com        (cpu_sequencers, dir_cntrls, topology) = \
11010116Snilay@cs.wisc.edu             eval("%s.create_system(options, system, dma_ports, ruby)"
1117557SBrad.Beckmann@amd.com                  % protocol)
1126923SBrad.Beckmann@amd.com    except:
1136923SBrad.Beckmann@amd.com        print "Error: could not create sytem for ruby protocol %s" % protocol
1147557SBrad.Beckmann@amd.com        raise
1158257SBrad.Beckmann@amd.com
1168706Sandreas.hansson@arm.com    # Create a port proxy for connecting the system port. This is
1178706Sandreas.hansson@arm.com    # independent of the protocol and kept in the protocol-agnostic
1188706Sandreas.hansson@arm.com    # part (i.e. here).
1198923Sandreas.hansson@arm.com    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
1208706Sandreas.hansson@arm.com    # Give the system port proxy a SimObject parent without creating a
1218706Sandreas.hansson@arm.com    # full-fledged controller
1228706Sandreas.hansson@arm.com    system.sys_port_proxy = sys_port_proxy
1238706Sandreas.hansson@arm.com
1248732Sandreas.hansson@arm.com    # Connect the system port for loading of binaries etc
1258839Sandreas.hansson@arm.com    system.system_port = system.sys_port_proxy.slave
1268732Sandreas.hansson@arm.com
1278732Sandreas.hansson@arm.com
1288257SBrad.Beckmann@amd.com    #
1298257SBrad.Beckmann@amd.com    # Set the network classes based on the command line options
1308257SBrad.Beckmann@amd.com    #
1318257SBrad.Beckmann@amd.com    if options.garnet_network == "fixed":
1328257SBrad.Beckmann@amd.com        class NetworkClass(GarnetNetwork_d): pass
1338257SBrad.Beckmann@amd.com        class IntLinkClass(GarnetIntLink_d): pass
1348257SBrad.Beckmann@amd.com        class ExtLinkClass(GarnetExtLink_d): pass
1358257SBrad.Beckmann@amd.com        class RouterClass(GarnetRouter_d): pass
1368257SBrad.Beckmann@amd.com    elif options.garnet_network == "flexible":
1378257SBrad.Beckmann@amd.com        class NetworkClass(GarnetNetwork): pass
1388257SBrad.Beckmann@amd.com        class IntLinkClass(GarnetIntLink): pass
1398257SBrad.Beckmann@amd.com        class ExtLinkClass(GarnetExtLink): pass
1408257SBrad.Beckmann@amd.com        class RouterClass(GarnetRouter): pass
1418257SBrad.Beckmann@amd.com    else:
1428257SBrad.Beckmann@amd.com        class NetworkClass(SimpleNetwork): pass
1438258SBrad.Beckmann@amd.com        class IntLinkClass(SimpleIntLink): pass
1448258SBrad.Beckmann@amd.com        class ExtLinkClass(SimpleExtLink): pass
1459274Snilay@cs.wisc.edu        class RouterClass(Switch): pass
1469148Spowerjg@cs.wisc.edu
1479148Spowerjg@cs.wisc.edu
1489862Snilay@cs.wisc.edu    # Create the network topology
1499862Snilay@cs.wisc.edu    network = NetworkClass(ruby_system = ruby, topology = topology.description,
1509862Snilay@cs.wisc.edu                           routers = [], ext_links = [], int_links = [])
1519862Snilay@cs.wisc.edu    topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
1529862Snilay@cs.wisc.edu                          RouterClass)
1538257SBrad.Beckmann@amd.com
1548612Stushar@csail.mit.edu    if options.network_fault_model:
1558612Stushar@csail.mit.edu        assert(options.garnet_network == "fixed")
1569593Snilay@cs.wisc.edu        network.enable_fault_model = True
1579593Snilay@cs.wisc.edu        network.fault_model = FaultModel()
1586892SBrad.Beckmann@amd.com
1596903SBrad.Beckmann@amd.com    #
1607563SBrad.Beckmann@amd.com    # Loop through the directory controlers.
1617025SBrad.Beckmann@amd.com    # Determine the total memory size of the ruby system and verify it is equal
1629148Spowerjg@cs.wisc.edu    # to physmem.  However, if Ruby memory is using sparse memory in SE
1637025SBrad.Beckmann@amd.com    # mode, then the system should not back-up the memory state with
1647025SBrad.Beckmann@amd.com    # the Memory Vector and thus the memory size bytes should stay at 0.
1657563SBrad.Beckmann@amd.com    # Also set the numa bits to the appropriate values.
1666903SBrad.Beckmann@amd.com    #
1676903SBrad.Beckmann@amd.com    total_mem_size = MemorySize('0B')
1687563SBrad.Beckmann@amd.com
1699318Spower.jg@gmail.com    ruby.block_size_bytes = options.cacheline_size
1709318Spower.jg@gmail.com    block_size_bits = int(math.log(options.cacheline_size, 2))
1717563SBrad.Beckmann@amd.com
1727563SBrad.Beckmann@amd.com    if options.numa_high_bit:
1737563SBrad.Beckmann@amd.com        numa_bit = options.numa_high_bit
1747563SBrad.Beckmann@amd.com    else:
1759318Spower.jg@gmail.com        # if the numa_bit is not specified, set the directory bits as the
1769318Spower.jg@gmail.com        # lowest bits above the block offset bits, and the numa_bit as the
1779318Spower.jg@gmail.com        # highest of those directory bits
17810004Snilay@cs.wisc.edu        dir_bits = int(math.log(options.num_dirs, 2))
1799318Spower.jg@gmail.com        numa_bit = block_size_bits + dir_bits - 1
1809148Spowerjg@cs.wisc.edu
1816903SBrad.Beckmann@amd.com    for dir_cntrl in dir_cntrls:
1826903SBrad.Beckmann@amd.com        total_mem_size.value += dir_cntrl.directory.size.value
1837563SBrad.Beckmann@amd.com        dir_cntrl.directory.numa_high_bit = numa_bit
1849148Spowerjg@cs.wisc.edu
1859826Sandreas.hansson@arm.com    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
1868931Sandreas.hansson@arm.com    assert(total_mem_size.value == phys_mem_size)
1876892SBrad.Beckmann@amd.com
1888436SBrad.Beckmann@amd.com    ruby.network = network
1898436SBrad.Beckmann@amd.com    ruby.mem_size = total_mem_size
19010116Snilay@cs.wisc.edu
19110116Snilay@cs.wisc.edu    # Connect the cpu sequencers and the piobus
19210116Snilay@cs.wisc.edu    if piobus != None:
19310116Snilay@cs.wisc.edu        for cpu_seq in cpu_sequencers:
19410116Snilay@cs.wisc.edu            cpu_seq.pio_master_port = piobus.slave
19510116Snilay@cs.wisc.edu            cpu_seq.mem_master_port = piobus.slave
19610116Snilay@cs.wisc.edu
19710116Snilay@cs.wisc.edu            if buildEnv['TARGET_ISA'] == "x86":
19810116Snilay@cs.wisc.edu                cpu_seq.pio_slave_port = piobus.master
19910116Snilay@cs.wisc.edu
2008322Ssteve.reinhardt@amd.com    ruby._cpu_ruby_ports = cpu_sequencers
20110012Snilay@cs.wisc.edu    ruby.num_of_sequencers = len(cpu_sequencers)
2027809Snilay@cs.wisc.edu    ruby.random_seed    = options.random_seed
203