MOESI_hammer.py revision 7561:02a9a597fce4
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import m5 31from m5.objects import * 32from m5.defines import buildEnv 33 34# 35# Note: the L1 Cache latency is only used by the sequencer on fast path hits 36# 37class L1Cache(RubyCache): 38 latency = 2 39 40# 41# Note: the L2 Cache latency is not currently used 42# 43class L2Cache(RubyCache): 44 latency = 10 45 46def define_options(parser): 47 parser.add_option("--allow-atomic-migration", action="store_true", 48 help="allow migratory sharing for atomic only accessed blocks") 49 50def create_system(options, system, piobus, dma_devices): 51 52 if buildEnv['PROTOCOL'] != 'MOESI_hammer': 53 panic("This script requires the MOESI_hammer protocol to be built.") 54 55 cpu_sequencers = [] 56 57 # 58 # The ruby network creation expects the list of nodes in the system to be 59 # consistent with the NetDest list. Therefore the l1 controller nodes must be 60 # listed before the directory nodes and directory nodes before dma nodes, etc. 61 # 62 l1_cntrl_nodes = [] 63 dir_cntrl_nodes = [] 64 dma_cntrl_nodes = [] 65 66 # 67 # Must create the individual controllers before the network to ensure the 68 # controller constructors are called before the network constructor 69 # 70 71 for i in xrange(options.num_cpus): 72 # 73 # First create the Ruby objects associated with this cpu 74 # 75 l1i_cache = L1Cache(size = options.l1i_size, 76 assoc = options.l1i_assoc) 77 l1d_cache = L1Cache(size = options.l1d_size, 78 assoc = options.l1d_assoc) 79 l2_cache = L2Cache(size = options.l2_size, 80 assoc = options.l2_assoc) 81 82 cpu_seq = RubySequencer(version = i, 83 icache = l1i_cache, 84 dcache = l1d_cache, 85 physMemPort = system.physmem.port, 86 physmem = system.physmem) 87 88 if piobus != None: 89 cpu_seq.pio_port = piobus.port 90 91 l1_cntrl = L1Cache_Controller(version = i, 92 sequencer = cpu_seq, 93 L1IcacheMemory = l1i_cache, 94 L1DcacheMemory = l1d_cache, 95 L2cacheMemory = l2_cache, 96 no_mig_atomic = not \ 97 options.allow_atomic_migration) 98 99 exec("system.l1_cntrl%d = l1_cntrl" % i) 100 # 101 # Add controllers and sequencers to the appropriate lists 102 # 103 cpu_sequencers.append(cpu_seq) 104 l1_cntrl_nodes.append(l1_cntrl) 105 106 phys_mem_size = long(system.physmem.range.second) - \ 107 long(system.physmem.range.first) + 1 108 mem_module_size = phys_mem_size / options.num_dirs 109 110 for i in xrange(options.num_dirs): 111 # 112 # Create the Ruby objects associated with the directory controller 113 # 114 115 mem_cntrl = RubyMemoryControl(version = i) 116 117 dir_size = MemorySize('0B') 118 dir_size.value = mem_module_size 119 120 dir_cntrl = Directory_Controller(version = i, 121 directory = \ 122 RubyDirectoryMemory( \ 123 version = i, 124 size = dir_size, 125 use_map = options.use_map, 126 map_levels = \ 127 options.map_levels), 128 memBuffer = mem_cntrl) 129 130 exec("system.dir_cntrl%d = dir_cntrl" % i) 131 dir_cntrl_nodes.append(dir_cntrl) 132 133 for i, dma_device in enumerate(dma_devices): 134 # 135 # Create the Ruby objects associated with the dma controller 136 # 137 dma_seq = DMASequencer(version = i, 138 physMemPort = system.physmem.port, 139 physmem = system.physmem) 140 141 dma_cntrl = DMA_Controller(version = i, 142 dma_sequencer = dma_seq) 143 144 exec("system.dma_cntrl%d = dma_cntrl" % i) 145 if dma_device.type == 'MemTest': 146 system.dma_cntrl.dma_sequencer.port = dma_device.test 147 else: 148 system.dma_cntrl.dma_sequencer.port = dma_device.dma 149 dma_cntrl.dma_sequencer.port = dma_device.dma 150 dma_cntrl_nodes.append(dma_cntrl) 151 152 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 153 154 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 155