MOESI_hammer.py revision 11022:e6e3b7097810
112855Sgabeblack@google.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 212855Sgabeblack@google.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 312855Sgabeblack@google.com# All rights reserved. 412855Sgabeblack@google.com# 512855Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 612855Sgabeblack@google.com# modification, are permitted provided that the following conditions are 712855Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 812855Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 912855Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 1012855Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 1112855Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 1212855Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 1312855Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 1412855Sgabeblack@google.com# this software without specific prior written permission. 1512855Sgabeblack@google.com# 1612855Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712855Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812855Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912855Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012855Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112855Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212855Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312855Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412855Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512855Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612855Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712855Sgabeblack@google.com# 2812855Sgabeblack@google.com# Authors: Brad Beckmann 2912855Sgabeblack@google.com 3012855Sgabeblack@google.comimport math 3112855Sgabeblack@google.comimport m5 3212855Sgabeblack@google.comfrom m5.objects import * 3312855Sgabeblack@google.comfrom m5.defines import buildEnv 3412855Sgabeblack@google.comfrom Ruby import create_topology 3512855Sgabeblack@google.comfrom Ruby import send_evicts 3612855Sgabeblack@google.com 3712855Sgabeblack@google.com# 3812855Sgabeblack@google.com# Declare caches used by the protocol 3912855Sgabeblack@google.com# 4012855Sgabeblack@google.comclass L1Cache(RubyCache): pass 4112855Sgabeblack@google.comclass L2Cache(RubyCache): pass 4212855Sgabeblack@google.com# 4312855Sgabeblack@google.com# Probe filter is a cache 4412855Sgabeblack@google.com# 4512855Sgabeblack@google.comclass ProbeFilter(RubyCache): pass 4612855Sgabeblack@google.com 4712855Sgabeblack@google.comdef define_options(parser): 4812855Sgabeblack@google.com parser.add_option("--allow-atomic-migration", action="store_true", 4912855Sgabeblack@google.com help="allow migratory sharing for atomic only accessed blocks") 5012855Sgabeblack@google.com parser.add_option("--pf-on", action="store_true", 5112855Sgabeblack@google.com help="Hammer: enable Probe Filter") 5212855Sgabeblack@google.com parser.add_option("--dir-on", action="store_true", 5312855Sgabeblack@google.com help="Hammer: enable Full-bit Directory") 5412855Sgabeblack@google.com 5512855Sgabeblack@google.comdef create_system(options, full_system, system, dma_ports, ruby_system): 5612855Sgabeblack@google.com 5712855Sgabeblack@google.com if buildEnv['PROTOCOL'] != 'MOESI_hammer': 5812855Sgabeblack@google.com panic("This script requires the MOESI_hammer protocol to be built.") 5912855Sgabeblack@google.com 6012855Sgabeblack@google.com cpu_sequencers = [] 6112855Sgabeblack@google.com 6212855Sgabeblack@google.com # 6312855Sgabeblack@google.com # The ruby network creation expects the list of nodes in the system to be 6412855Sgabeblack@google.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 6512855Sgabeblack@google.com # listed before the directory nodes and directory nodes before dma nodes, etc. 6612855Sgabeblack@google.com # 6712855Sgabeblack@google.com l1_cntrl_nodes = [] 6812855Sgabeblack@google.com dir_cntrl_nodes = [] 6912855Sgabeblack@google.com dma_cntrl_nodes = [] 7012855Sgabeblack@google.com 7112855Sgabeblack@google.com # 7212855Sgabeblack@google.com # Must create the individual controllers before the network to ensure the 7312855Sgabeblack@google.com # controller constructors are called before the network constructor 7412855Sgabeblack@google.com # 7512855Sgabeblack@google.com block_size_bits = int(math.log(options.cacheline_size, 2)) 7612855Sgabeblack@google.com 7712855Sgabeblack@google.com for i in xrange(options.num_cpus): 7812855Sgabeblack@google.com # 7912855Sgabeblack@google.com # First create the Ruby objects associated with this cpu 8012855Sgabeblack@google.com # 8112855Sgabeblack@google.com l1i_cache = L1Cache(size = options.l1i_size, 8212855Sgabeblack@google.com assoc = options.l1i_assoc, 8312855Sgabeblack@google.com start_index_bit = block_size_bits, 8412855Sgabeblack@google.com is_icache = True) 8512855Sgabeblack@google.com l1d_cache = L1Cache(size = options.l1d_size, 8612855Sgabeblack@google.com assoc = options.l1d_assoc, 8712855Sgabeblack@google.com start_index_bit = block_size_bits) 8812855Sgabeblack@google.com l2_cache = L2Cache(size = options.l2_size, 8912855Sgabeblack@google.com assoc = options.l2_assoc, 9012855Sgabeblack@google.com start_index_bit = block_size_bits) 9112855Sgabeblack@google.com 9212855Sgabeblack@google.com l1_cntrl = L1Cache_Controller(version = i, 9312855Sgabeblack@google.com L1Icache = l1i_cache, 9412855Sgabeblack@google.com L1Dcache = l1d_cache, 9512855Sgabeblack@google.com L2cache = l2_cache, 9612855Sgabeblack@google.com no_mig_atomic = not \ 9712855Sgabeblack@google.com options.allow_atomic_migration, 9812855Sgabeblack@google.com send_evictions = send_evicts(options), 9912855Sgabeblack@google.com transitions_per_cycle = options.ports, 10012855Sgabeblack@google.com clk_domain=system.cpu[i].clk_domain, 10112855Sgabeblack@google.com ruby_system = ruby_system) 10212855Sgabeblack@google.com 10312855Sgabeblack@google.com cpu_seq = RubySequencer(version = i, 10412855Sgabeblack@google.com icache = l1i_cache, 10512855Sgabeblack@google.com dcache = l1d_cache, 10612855Sgabeblack@google.com clk_domain=system.cpu[i].clk_domain, 10712855Sgabeblack@google.com ruby_system = ruby_system) 10812855Sgabeblack@google.com 10912855Sgabeblack@google.com l1_cntrl.sequencer = cpu_seq 11012855Sgabeblack@google.com if options.recycle_latency: 11112855Sgabeblack@google.com l1_cntrl.recycle_latency = options.recycle_latency 112 113 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 114 115 # Add controllers and sequencers to the appropriate lists 116 cpu_sequencers.append(cpu_seq) 117 l1_cntrl_nodes.append(l1_cntrl) 118 119 # Connect the L1 controller and the network 120 # Connect the buffers from the controller to network 121 l1_cntrl.requestFromCache = MessageBuffer() 122 l1_cntrl.requestFromCache.master = ruby_system.network.slave 123 l1_cntrl.responseFromCache = MessageBuffer() 124 l1_cntrl.responseFromCache.master = ruby_system.network.slave 125 l1_cntrl.unblockFromCache = MessageBuffer() 126 l1_cntrl.unblockFromCache.master = ruby_system.network.slave 127 128 l1_cntrl.triggerQueue = MessageBuffer() 129 130 # Connect the buffers from the network to the controller 131 l1_cntrl.mandatoryQueue = MessageBuffer() 132 l1_cntrl.forwardToCache = MessageBuffer() 133 l1_cntrl.forwardToCache.slave = ruby_system.network.master 134 l1_cntrl.responseToCache = MessageBuffer() 135 l1_cntrl.responseToCache.slave = ruby_system.network.master 136 137 138 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 139 assert(phys_mem_size % options.num_dirs == 0) 140 mem_module_size = phys_mem_size / options.num_dirs 141 142 # 143 # determine size and index bits for probe filter 144 # By default, the probe filter size is configured to be twice the 145 # size of the L2 cache. 146 # 147 pf_size = MemorySize(options.l2_size) 148 pf_size.value = pf_size.value * 2 149 dir_bits = int(math.log(options.num_dirs, 2)) 150 pf_bits = int(math.log(pf_size.value, 2)) 151 if options.numa_high_bit: 152 if options.pf_on or options.dir_on: 153 # if numa high bit explicitly set, make sure it does not overlap 154 # with the probe filter index 155 assert(options.numa_high_bit - dir_bits > pf_bits) 156 157 # set the probe filter start bit to just above the block offset 158 pf_start_bit = block_size_bits 159 else: 160 if dir_bits > 0: 161 pf_start_bit = dir_bits + block_size_bits - 1 162 else: 163 pf_start_bit = block_size_bits 164 165 # Run each of the ruby memory controllers at a ratio of the frequency of 166 # the ruby system 167 # clk_divider value is a fix to pass regression. 168 ruby_system.memctrl_clk_domain = DerivedClockDomain( 169 clk_domain=ruby_system.clk_domain, 170 clk_divider=3) 171 172 for i in xrange(options.num_dirs): 173 dir_size = MemorySize('0B') 174 dir_size.value = mem_module_size 175 176 pf = ProbeFilter(size = pf_size, assoc = 4, 177 start_index_bit = pf_start_bit) 178 179 dir_cntrl = Directory_Controller(version = i, 180 directory = RubyDirectoryMemory( 181 version = i, size = dir_size), 182 probeFilter = pf, 183 probe_filter_enabled = options.pf_on, 184 full_bit_dir_enabled = options.dir_on, 185 transitions_per_cycle = options.ports, 186 ruby_system = ruby_system) 187 188 if options.recycle_latency: 189 dir_cntrl.recycle_latency = options.recycle_latency 190 191 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 192 dir_cntrl_nodes.append(dir_cntrl) 193 194 # Connect the directory controller to the network 195 dir_cntrl.forwardFromDir = MessageBuffer() 196 dir_cntrl.forwardFromDir.master = ruby_system.network.slave 197 dir_cntrl.responseFromDir = MessageBuffer() 198 dir_cntrl.responseFromDir.master = ruby_system.network.slave 199 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) 200 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave 201 202 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 203 204 dir_cntrl.unblockToDir = MessageBuffer() 205 dir_cntrl.unblockToDir.slave = ruby_system.network.master 206 dir_cntrl.responseToDir = MessageBuffer() 207 dir_cntrl.responseToDir.slave = ruby_system.network.master 208 dir_cntrl.requestToDir = MessageBuffer() 209 dir_cntrl.requestToDir.slave = ruby_system.network.master 210 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) 211 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master 212 dir_cntrl.responseFromMemory = MessageBuffer() 213 214 215 for i, dma_port in enumerate(dma_ports): 216 # 217 # Create the Ruby objects associated with the dma controller 218 # 219 dma_seq = DMASequencer(version = i, 220 ruby_system = ruby_system, 221 slave = dma_port) 222 223 dma_cntrl = DMA_Controller(version = i, 224 dma_sequencer = dma_seq, 225 transitions_per_cycle = options.ports, 226 ruby_system = ruby_system) 227 228 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 229 dma_cntrl_nodes.append(dma_cntrl) 230 231 if options.recycle_latency: 232 dma_cntrl.recycle_latency = options.recycle_latency 233 234 # Connect the dma controller to the network 235 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 236 dma_cntrl.responseFromDir.slave = ruby_system.network.master 237 dma_cntrl.requestToDir = MessageBuffer() 238 dma_cntrl.requestToDir.master = ruby_system.network.slave 239 dma_cntrl.mandatoryQueue = MessageBuffer() 240 241 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 242 243 # Create the io controller and the sequencer 244 if full_system: 245 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 246 ruby_system._io_port = io_seq 247 io_controller = DMA_Controller(version = len(dma_ports), 248 dma_sequencer = io_seq, 249 ruby_system = ruby_system) 250 ruby_system.io_controller = io_controller 251 252 # Connect the dma controller to the network 253 io_controller.responseFromDir = MessageBuffer(ordered = True) 254 io_controller.responseFromDir.slave = ruby_system.network.master 255 io_controller.requestToDir = MessageBuffer() 256 io_controller.requestToDir.master = ruby_system.network.slave 257 io_controller.mandatoryQueue = MessageBuffer() 258 259 all_cntrls = all_cntrls + [io_controller] 260 261 topology = create_topology(all_cntrls, options) 262 return (cpu_sequencers, dir_cntrl_nodes, topology) 263