MOESI_hammer.py revision 11019:fc1e41e88fd3 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35from Ruby import send_evicts
36
37#
38# Declare caches used by the protocol
39#
40class L1Cache(RubyCache): pass
41class L2Cache(RubyCache): pass
42#
43# Probe filter is a cache
44#
45class ProbeFilter(RubyCache): pass
46
47def define_options(parser):
48    parser.add_option("--allow-atomic-migration", action="store_true",
49          help="allow migratory sharing for atomic only accessed blocks")
50    parser.add_option("--pf-on", action="store_true",
51          help="Hammer: enable Probe Filter")
52    parser.add_option("--dir-on", action="store_true",
53          help="Hammer: enable Full-bit Directory")
54
55def create_system(options, full_system, system, dma_ports, ruby_system):
56
57    if buildEnv['PROTOCOL'] != 'MOESI_hammer':
58        panic("This script requires the MOESI_hammer protocol to be built.")
59
60    cpu_sequencers = []
61
62    #
63    # The ruby network creation expects the list of nodes in the system to be
64    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
65    # listed before the directory nodes and directory nodes before dma nodes, etc.
66    #
67    l1_cntrl_nodes = []
68    dir_cntrl_nodes = []
69    dma_cntrl_nodes = []
70
71    #
72    # Must create the individual controllers before the network to ensure the
73    # controller constructors are called before the network constructor
74    #
75    block_size_bits = int(math.log(options.cacheline_size, 2))
76
77    for i in xrange(options.num_cpus):
78        #
79        # First create the Ruby objects associated with this cpu
80        #
81        l1i_cache = L1Cache(size = options.l1i_size,
82                            assoc = options.l1i_assoc,
83                            start_index_bit = block_size_bits,
84                            is_icache = True)
85        l1d_cache = L1Cache(size = options.l1d_size,
86                            assoc = options.l1d_assoc,
87                            start_index_bit = block_size_bits)
88        l2_cache = L2Cache(size = options.l2_size,
89                           assoc = options.l2_assoc,
90                           start_index_bit = block_size_bits)
91
92        l1_cntrl = L1Cache_Controller(version = i,
93                                      L1Icache = l1i_cache,
94                                      L1Dcache = l1d_cache,
95                                      L2cache = l2_cache,
96                                      no_mig_atomic = not \
97                                        options.allow_atomic_migration,
98                                      send_evictions = send_evicts(options),
99                                      transitions_per_cycle = options.ports,
100                                      clk_domain=system.cpu[i].clk_domain,
101                                      ruby_system = ruby_system)
102
103        cpu_seq = RubySequencer(version = i,
104                                icache = l1i_cache,
105                                dcache = l1d_cache,
106                                clk_domain=system.cpu[i].clk_domain,
107                                ruby_system = ruby_system)
108
109        l1_cntrl.sequencer = cpu_seq
110        if options.recycle_latency:
111            l1_cntrl.recycle_latency = options.recycle_latency
112
113        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
114
115        # Add controllers and sequencers to the appropriate lists
116        cpu_sequencers.append(cpu_seq)
117        l1_cntrl_nodes.append(l1_cntrl)
118
119        # Connect the L1 controller and the network
120        # Connect the buffers from the controller to network
121        l1_cntrl.requestFromCache = ruby_system.network.slave
122        l1_cntrl.responseFromCache = ruby_system.network.slave
123        l1_cntrl.unblockFromCache = ruby_system.network.slave
124
125        # Connect the buffers from the network to the controller
126        l1_cntrl.forwardToCache = ruby_system.network.master
127        l1_cntrl.responseToCache = ruby_system.network.master
128
129
130    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
131    assert(phys_mem_size % options.num_dirs == 0)
132    mem_module_size = phys_mem_size / options.num_dirs
133
134    #
135    # determine size and index bits for probe filter
136    # By default, the probe filter size is configured to be twice the
137    # size of the L2 cache.
138    #
139    pf_size = MemorySize(options.l2_size)
140    pf_size.value = pf_size.value * 2
141    dir_bits = int(math.log(options.num_dirs, 2))
142    pf_bits = int(math.log(pf_size.value, 2))
143    if options.numa_high_bit:
144        if options.pf_on or options.dir_on:
145            # if numa high bit explicitly set, make sure it does not overlap
146            # with the probe filter index
147            assert(options.numa_high_bit - dir_bits > pf_bits)
148
149        # set the probe filter start bit to just above the block offset
150        pf_start_bit = block_size_bits
151    else:
152        if dir_bits > 0:
153            pf_start_bit = dir_bits + block_size_bits - 1
154        else:
155            pf_start_bit = block_size_bits
156
157    # Run each of the ruby memory controllers at a ratio of the frequency of
158    # the ruby system
159    # clk_divider value is a fix to pass regression.
160    ruby_system.memctrl_clk_domain = DerivedClockDomain(
161                                          clk_domain=ruby_system.clk_domain,
162                                          clk_divider=3)
163
164    for i in xrange(options.num_dirs):
165        dir_size = MemorySize('0B')
166        dir_size.value = mem_module_size
167
168        pf = ProbeFilter(size = pf_size, assoc = 4,
169                         start_index_bit = pf_start_bit)
170
171        dir_cntrl = Directory_Controller(version = i,
172                                         directory = RubyDirectoryMemory(
173                                            version = i, size = dir_size),
174                                         probeFilter = pf,
175                                         probe_filter_enabled = options.pf_on,
176                                         full_bit_dir_enabled = options.dir_on,
177                                         transitions_per_cycle = options.ports,
178                                         ruby_system = ruby_system)
179
180        if options.recycle_latency:
181            dir_cntrl.recycle_latency = options.recycle_latency
182
183        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
184        dir_cntrl_nodes.append(dir_cntrl)
185
186        # Connect the directory controller to the network
187        dir_cntrl.forwardFromDir = ruby_system.network.slave
188        dir_cntrl.responseFromDir = ruby_system.network.slave
189        dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
190
191        dir_cntrl.unblockToDir = ruby_system.network.master
192        dir_cntrl.responseToDir = ruby_system.network.master
193        dir_cntrl.requestToDir = ruby_system.network.master
194        dir_cntrl.dmaRequestToDir = ruby_system.network.master
195
196
197    for i, dma_port in enumerate(dma_ports):
198        #
199        # Create the Ruby objects associated with the dma controller
200        #
201        dma_seq = DMASequencer(version = i,
202                               ruby_system = ruby_system,
203                               slave = dma_port)
204
205        dma_cntrl = DMA_Controller(version = i,
206                                   dma_sequencer = dma_seq,
207                                   transitions_per_cycle = options.ports,
208                                   ruby_system = ruby_system)
209
210        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
211        dma_cntrl_nodes.append(dma_cntrl)
212
213        if options.recycle_latency:
214            dma_cntrl.recycle_latency = options.recycle_latency
215
216        # Connect the dma controller to the network
217        dma_cntrl.responseFromDir = ruby_system.network.master
218        dma_cntrl.requestToDir = ruby_system.network.slave
219
220    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
221
222    # Create the io controller and the sequencer
223    if full_system:
224        io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
225        ruby_system._io_port = io_seq
226        io_controller = DMA_Controller(version = len(dma_ports),
227                                       dma_sequencer = io_seq,
228                                       ruby_system = ruby_system)
229        ruby_system.io_controller = io_controller
230
231        # Connect the dma controller to the network
232        io_controller.responseFromDir = ruby_system.network.master
233        io_controller.requestToDir = ruby_system.network.slave
234
235        all_cntrls = all_cntrls + [io_controller]
236
237    topology = create_topology(all_cntrls, options)
238    return (cpu_sequencers, dir_cntrl_nodes, topology)
239