MOESI_hammer.py revision 9318
16892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36892SBrad.Beckmann@amd.com# All rights reserved. 46892SBrad.Beckmann@amd.com# 56892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com# this software without specific prior written permission. 156892SBrad.Beckmann@amd.com# 166892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296892SBrad.Beckmann@amd.com 307564SBrad.Beckmann@amd.comimport math 316892SBrad.Beckmann@amd.comimport m5 326892SBrad.Beckmann@amd.comfrom m5.objects import * 336892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 356892SBrad.Beckmann@amd.com 366892SBrad.Beckmann@amd.com# 376892SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 386892SBrad.Beckmann@amd.com# 396892SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 407551SBrad.Beckmann@amd.com latency = 2 416892SBrad.Beckmann@amd.com 426892SBrad.Beckmann@amd.com# 436892SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 446892SBrad.Beckmann@amd.com# 456892SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 467551SBrad.Beckmann@amd.com latency = 10 476892SBrad.Beckmann@amd.com 487564SBrad.Beckmann@amd.com# 497564SBrad.Beckmann@amd.com# Probe filter is a cache, latency is not used 507564SBrad.Beckmann@amd.com# 517564SBrad.Beckmann@amd.comclass ProbeFilter(RubyCache): 527564SBrad.Beckmann@amd.com latency = 1 537564SBrad.Beckmann@amd.com 547538SBrad.Beckmann@amd.comdef define_options(parser): 557561SBrad.Beckmann@amd.com parser.add_option("--allow-atomic-migration", action="store_true", 567561SBrad.Beckmann@amd.com help="allow migratory sharing for atomic only accessed blocks") 577564SBrad.Beckmann@amd.com parser.add_option("--pf-on", action="store_true", 587564SBrad.Beckmann@amd.com help="Hammer: enable Probe Filter") 597904SBrad.Beckmann@amd.com parser.add_option("--dir-on", action="store_true", 607904SBrad.Beckmann@amd.com help="Hammer: enable Full-bit Directory") 617904SBrad.Beckmann@amd.com 628929Snilay@cs.wisc.edudef create_system(options, system, piobus, dma_ports, ruby_system): 638436SBrad.Beckmann@amd.com 646892SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_hammer': 656892SBrad.Beckmann@amd.com panic("This script requires the MOESI_hammer protocol to be built.") 666892SBrad.Beckmann@amd.com 676893SBrad.Beckmann@amd.com cpu_sequencers = [] 686893SBrad.Beckmann@amd.com 696892SBrad.Beckmann@amd.com # 706892SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 716892SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 726892SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 736892SBrad.Beckmann@amd.com # 746892SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 756892SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 766892SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 776892SBrad.Beckmann@amd.com 786892SBrad.Beckmann@amd.com # 796892SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 806892SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 816892SBrad.Beckmann@amd.com # 828180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 838257SBrad.Beckmann@amd.com 848257SBrad.Beckmann@amd.com cntrl_count = 0 856893SBrad.Beckmann@amd.com 866893SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 876892SBrad.Beckmann@amd.com # 886892SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 896892SBrad.Beckmann@amd.com # 906903SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 918180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 928653Snilay@cs.wisc.edu start_index_bit = block_size_bits, 938653Snilay@cs.wisc.edu is_icache = True) 946903SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 958180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 968180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 976903SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 988180SBrad.Beckmann@amd.com assoc = options.l2_assoc, 998180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 1006892SBrad.Beckmann@amd.com 1018322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 1028322Ssteve.reinhardt@amd.com cntrl_id = cntrl_count, 1038322Ssteve.reinhardt@amd.com L1IcacheMemory = l1i_cache, 1048322Ssteve.reinhardt@amd.com L1DcacheMemory = l1d_cache, 1058322Ssteve.reinhardt@amd.com L2cacheMemory = l2_cache, 1068322Ssteve.reinhardt@amd.com no_mig_atomic = not \ 1078436SBrad.Beckmann@amd.com options.allow_atomic_migration, 1088717Snilay@cs.wisc.edu send_evictions = ( 1098717Snilay@cs.wisc.edu options.cpu_type == "detailed"), 1108436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1118322Ssteve.reinhardt@amd.com 1127015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 1137015SBrad.Beckmann@amd.com icache = l1i_cache, 1146892SBrad.Beckmann@amd.com dcache = l1d_cache, 1158436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1166893SBrad.Beckmann@amd.com 1178322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 1188322Ssteve.reinhardt@amd.com 1196893SBrad.Beckmann@amd.com if piobus != None: 1208845Sandreas.hansson@arm.com cpu_seq.pio_port = piobus.slave 1216892SBrad.Beckmann@amd.com 1227566SBrad.Beckmann@amd.com if options.recycle_latency: 1237566SBrad.Beckmann@amd.com l1_cntrl.recycle_latency = options.recycle_latency 1247566SBrad.Beckmann@amd.com 1257541SBrad.Beckmann@amd.com exec("system.l1_cntrl%d = l1_cntrl" % i) 1266893SBrad.Beckmann@amd.com # 1276893SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1286893SBrad.Beckmann@amd.com # 1296893SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1306893SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1316893SBrad.Beckmann@amd.com 1328257SBrad.Beckmann@amd.com cntrl_count += 1 1338257SBrad.Beckmann@amd.com 1349232Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda mem: mem.range.size(), 1359232Sandreas.hansson@arm.com system.memories.unproxy(system))) 1366905SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1376905SBrad.Beckmann@amd.com 1387564SBrad.Beckmann@amd.com # 1397564SBrad.Beckmann@amd.com # determine size and index bits for probe filter 1407564SBrad.Beckmann@amd.com # By default, the probe filter size is configured to be twice the 1417564SBrad.Beckmann@amd.com # size of the L2 cache. 1427564SBrad.Beckmann@amd.com # 1437564SBrad.Beckmann@amd.com pf_size = MemorySize(options.l2_size) 1447564SBrad.Beckmann@amd.com pf_size.value = pf_size.value * 2 1457564SBrad.Beckmann@amd.com dir_bits = int(math.log(options.num_dirs, 2)) 1467564SBrad.Beckmann@amd.com pf_bits = int(math.log(pf_size.value, 2)) 1477564SBrad.Beckmann@amd.com if options.numa_high_bit: 1489318Spower.jg@gmail.com if options.pf_on or options.dir_on: 1497564SBrad.Beckmann@amd.com # if numa high bit explicitly set, make sure it does not overlap 1507564SBrad.Beckmann@amd.com # with the probe filter index 1517564SBrad.Beckmann@amd.com assert(options.numa_high_bit - dir_bits > pf_bits) 1527564SBrad.Beckmann@amd.com 1537564SBrad.Beckmann@amd.com # set the probe filter start bit to just above the block offset 1549318Spower.jg@gmail.com pf_start_bit = block_size_bits 1557564SBrad.Beckmann@amd.com else: 1567564SBrad.Beckmann@amd.com if dir_bits > 0: 1579318Spower.jg@gmail.com pf_start_bit = dir_bits + block_size_bits - 1 1587564SBrad.Beckmann@amd.com else: 1599318Spower.jg@gmail.com pf_start_bit = block_size_bits 1607564SBrad.Beckmann@amd.com 1616893SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1626893SBrad.Beckmann@amd.com # 1636893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1646893SBrad.Beckmann@amd.com # 1656892SBrad.Beckmann@amd.com 1669154Spower.jg@gmail.com mem_cntrl = RubyMemoryControl(version = i, 1679154Spower.jg@gmail.com ruby_system = ruby_system) 1686892SBrad.Beckmann@amd.com 1696905SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1706905SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1716905SBrad.Beckmann@amd.com 1727662SBrad.Beckmann@amd.com pf = ProbeFilter(size = pf_size, assoc = 4, 1737662SBrad.Beckmann@amd.com start_index_bit = pf_start_bit) 1747564SBrad.Beckmann@amd.com 1756892SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1768257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 1776893SBrad.Beckmann@amd.com directory = \ 1787541SBrad.Beckmann@amd.com RubyDirectoryMemory( \ 1797541SBrad.Beckmann@amd.com version = i, 1807541SBrad.Beckmann@amd.com size = dir_size, 1817541SBrad.Beckmann@amd.com use_map = options.use_map, 1827541SBrad.Beckmann@amd.com map_levels = \ 1837917SBrad.Beckmann@amd.com options.map_levels, 1847917SBrad.Beckmann@amd.com numa_high_bit = \ 1857917SBrad.Beckmann@amd.com options.numa_high_bit), 1867564SBrad.Beckmann@amd.com probeFilter = pf, 1877564SBrad.Beckmann@amd.com memBuffer = mem_cntrl, 1887904SBrad.Beckmann@amd.com probe_filter_enabled = options.pf_on, 1898436SBrad.Beckmann@amd.com full_bit_dir_enabled = options.dir_on, 1908436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1916892SBrad.Beckmann@amd.com 1927566SBrad.Beckmann@amd.com if options.recycle_latency: 1937566SBrad.Beckmann@amd.com dir_cntrl.recycle_latency = options.recycle_latency 1947566SBrad.Beckmann@amd.com 1957541SBrad.Beckmann@amd.com exec("system.dir_cntrl%d = dir_cntrl" % i) 1966893SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1976893SBrad.Beckmann@amd.com 1988257SBrad.Beckmann@amd.com cntrl_count += 1 1998257SBrad.Beckmann@amd.com 2008929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 2016893SBrad.Beckmann@amd.com # 2026893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 2036893SBrad.Beckmann@amd.com # 2046893SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 2058477Snilay@cs.wisc.edu ruby_system = ruby_system) 2066893SBrad.Beckmann@amd.com 2076892SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 2088257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 2098477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 2108477Snilay@cs.wisc.edu ruby_system = ruby_system) 2116892SBrad.Beckmann@amd.com 2127541SBrad.Beckmann@amd.com exec("system.dma_cntrl%d = dma_cntrl" % i) 2138929Snilay@cs.wisc.edu exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 2146892SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 2156892SBrad.Beckmann@amd.com 2167566SBrad.Beckmann@amd.com if options.recycle_latency: 2177566SBrad.Beckmann@amd.com dma_cntrl.recycle_latency = options.recycle_latency 2187566SBrad.Beckmann@amd.com 2198257SBrad.Beckmann@amd.com cntrl_count += 1 2208257SBrad.Beckmann@amd.com 2216892SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 2226892SBrad.Beckmann@amd.com 2239100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 2249100SBrad.Beckmann@amd.com 2259100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 226