MOESI_hammer.py revision 7917
16892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36892SBrad.Beckmann@amd.com# All rights reserved. 46892SBrad.Beckmann@amd.com# 56892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com# this software without specific prior written permission. 156892SBrad.Beckmann@amd.com# 166892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296892SBrad.Beckmann@amd.com 307564SBrad.Beckmann@amd.comimport math 316892SBrad.Beckmann@amd.comimport m5 326892SBrad.Beckmann@amd.comfrom m5.objects import * 336892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 346892SBrad.Beckmann@amd.com 356892SBrad.Beckmann@amd.com# 366892SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 376892SBrad.Beckmann@amd.com# 386892SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 397551SBrad.Beckmann@amd.com latency = 2 406892SBrad.Beckmann@amd.com 416892SBrad.Beckmann@amd.com# 426892SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 436892SBrad.Beckmann@amd.com# 446892SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 457551SBrad.Beckmann@amd.com latency = 10 466892SBrad.Beckmann@amd.com 477564SBrad.Beckmann@amd.com# 487564SBrad.Beckmann@amd.com# Probe filter is a cache, latency is not used 497564SBrad.Beckmann@amd.com# 507564SBrad.Beckmann@amd.comclass ProbeFilter(RubyCache): 517564SBrad.Beckmann@amd.com latency = 1 527564SBrad.Beckmann@amd.com 537538SBrad.Beckmann@amd.comdef define_options(parser): 547561SBrad.Beckmann@amd.com parser.add_option("--allow-atomic-migration", action="store_true", 557561SBrad.Beckmann@amd.com help="allow migratory sharing for atomic only accessed blocks") 567564SBrad.Beckmann@amd.com parser.add_option("--pf-on", action="store_true", 577564SBrad.Beckmann@amd.com help="Hammer: enable Probe Filter") 587904SBrad.Beckmann@amd.com parser.add_option("--dir-on", action="store_true", 597904SBrad.Beckmann@amd.com help="Hammer: enable Full-bit Directory") 607904SBrad.Beckmann@amd.com 617541SBrad.Beckmann@amd.comdef create_system(options, system, piobus, dma_devices): 626892SBrad.Beckmann@amd.com 636892SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_hammer': 646892SBrad.Beckmann@amd.com panic("This script requires the MOESI_hammer protocol to be built.") 656892SBrad.Beckmann@amd.com 666893SBrad.Beckmann@amd.com cpu_sequencers = [] 676893SBrad.Beckmann@amd.com 686892SBrad.Beckmann@amd.com # 696892SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 706892SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 716892SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 726892SBrad.Beckmann@amd.com # 736892SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 746892SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 756892SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 766892SBrad.Beckmann@amd.com 776892SBrad.Beckmann@amd.com # 786892SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 796892SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 806892SBrad.Beckmann@amd.com # 816893SBrad.Beckmann@amd.com 826893SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 836892SBrad.Beckmann@amd.com # 846892SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 856892SBrad.Beckmann@amd.com # 866903SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 876903SBrad.Beckmann@amd.com assoc = options.l1i_assoc) 886903SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 896903SBrad.Beckmann@amd.com assoc = options.l1d_assoc) 906903SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 916903SBrad.Beckmann@amd.com assoc = options.l2_assoc) 926892SBrad.Beckmann@amd.com 937015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 947015SBrad.Beckmann@amd.com icache = l1i_cache, 956892SBrad.Beckmann@amd.com dcache = l1d_cache, 967541SBrad.Beckmann@amd.com physMemPort = system.physmem.port, 977541SBrad.Beckmann@amd.com physmem = system.physmem) 986893SBrad.Beckmann@amd.com 996893SBrad.Beckmann@amd.com if piobus != None: 1006893SBrad.Beckmann@amd.com cpu_seq.pio_port = piobus.port 1016892SBrad.Beckmann@amd.com 1026892SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 1036892SBrad.Beckmann@amd.com sequencer = cpu_seq, 1046892SBrad.Beckmann@amd.com L1IcacheMemory = l1i_cache, 1056892SBrad.Beckmann@amd.com L1DcacheMemory = l1d_cache, 1067561SBrad.Beckmann@amd.com L2cacheMemory = l2_cache, 1077561SBrad.Beckmann@amd.com no_mig_atomic = not \ 1087561SBrad.Beckmann@amd.com options.allow_atomic_migration) 1097541SBrad.Beckmann@amd.com 1107566SBrad.Beckmann@amd.com if options.recycle_latency: 1117566SBrad.Beckmann@amd.com l1_cntrl.recycle_latency = options.recycle_latency 1127566SBrad.Beckmann@amd.com 1137541SBrad.Beckmann@amd.com exec("system.l1_cntrl%d = l1_cntrl" % i) 1146893SBrad.Beckmann@amd.com # 1156893SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1166893SBrad.Beckmann@amd.com # 1176893SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1186893SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1196893SBrad.Beckmann@amd.com 1207541SBrad.Beckmann@amd.com phys_mem_size = long(system.physmem.range.second) - \ 1217541SBrad.Beckmann@amd.com long(system.physmem.range.first) + 1 1226905SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1236905SBrad.Beckmann@amd.com 1247564SBrad.Beckmann@amd.com # 1257564SBrad.Beckmann@amd.com # determine size and index bits for probe filter 1267564SBrad.Beckmann@amd.com # By default, the probe filter size is configured to be twice the 1277564SBrad.Beckmann@amd.com # size of the L2 cache. 1287564SBrad.Beckmann@amd.com # 1297564SBrad.Beckmann@amd.com pf_size = MemorySize(options.l2_size) 1307564SBrad.Beckmann@amd.com pf_size.value = pf_size.value * 2 1317564SBrad.Beckmann@amd.com dir_bits = int(math.log(options.num_dirs, 2)) 1327564SBrad.Beckmann@amd.com pf_bits = int(math.log(pf_size.value, 2)) 1337564SBrad.Beckmann@amd.com if options.numa_high_bit: 1347564SBrad.Beckmann@amd.com if options.numa_high_bit > 0: 1357564SBrad.Beckmann@amd.com # if numa high bit explicitly set, make sure it does not overlap 1367564SBrad.Beckmann@amd.com # with the probe filter index 1377564SBrad.Beckmann@amd.com assert(options.numa_high_bit - dir_bits > pf_bits) 1387564SBrad.Beckmann@amd.com 1397564SBrad.Beckmann@amd.com # set the probe filter start bit to just above the block offset 1407564SBrad.Beckmann@amd.com pf_start_bit = 6 1417564SBrad.Beckmann@amd.com else: 1427564SBrad.Beckmann@amd.com if dir_bits > 0: 1437564SBrad.Beckmann@amd.com pf_start_bit = dir_bits + 5 1447564SBrad.Beckmann@amd.com else: 1457564SBrad.Beckmann@amd.com pf_start_bit = 6 1467564SBrad.Beckmann@amd.com 1476893SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1486893SBrad.Beckmann@amd.com # 1496893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1506893SBrad.Beckmann@amd.com # 1516892SBrad.Beckmann@amd.com 1526892SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 1536892SBrad.Beckmann@amd.com 1546905SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1556905SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1566905SBrad.Beckmann@amd.com 1577662SBrad.Beckmann@amd.com pf = ProbeFilter(size = pf_size, assoc = 4, 1587662SBrad.Beckmann@amd.com start_index_bit = pf_start_bit) 1597564SBrad.Beckmann@amd.com 1606892SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1616893SBrad.Beckmann@amd.com directory = \ 1627541SBrad.Beckmann@amd.com RubyDirectoryMemory( \ 1637541SBrad.Beckmann@amd.com version = i, 1647541SBrad.Beckmann@amd.com size = dir_size, 1657541SBrad.Beckmann@amd.com use_map = options.use_map, 1667541SBrad.Beckmann@amd.com map_levels = \ 1677917SBrad.Beckmann@amd.com options.map_levels, 1687917SBrad.Beckmann@amd.com numa_high_bit = \ 1697917SBrad.Beckmann@amd.com options.numa_high_bit), 1707564SBrad.Beckmann@amd.com probeFilter = pf, 1717564SBrad.Beckmann@amd.com memBuffer = mem_cntrl, 1727904SBrad.Beckmann@amd.com probe_filter_enabled = options.pf_on, 1737904SBrad.Beckmann@amd.com full_bit_dir_enabled = options.dir_on) 1746892SBrad.Beckmann@amd.com 1757566SBrad.Beckmann@amd.com if options.recycle_latency: 1767566SBrad.Beckmann@amd.com dir_cntrl.recycle_latency = options.recycle_latency 1777566SBrad.Beckmann@amd.com 1787541SBrad.Beckmann@amd.com exec("system.dir_cntrl%d = dir_cntrl" % i) 1796893SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1806893SBrad.Beckmann@amd.com 1816893SBrad.Beckmann@amd.com for i, dma_device in enumerate(dma_devices): 1826893SBrad.Beckmann@amd.com # 1836893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1846893SBrad.Beckmann@amd.com # 1856893SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1867541SBrad.Beckmann@amd.com physMemPort = system.physmem.port, 1877541SBrad.Beckmann@amd.com physmem = system.physmem) 1886893SBrad.Beckmann@amd.com 1896892SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1906893SBrad.Beckmann@amd.com dma_sequencer = dma_seq) 1916892SBrad.Beckmann@amd.com 1927541SBrad.Beckmann@amd.com exec("system.dma_cntrl%d = dma_cntrl" % i) 1937544SBrad.Beckmann@amd.com if dma_device.type == 'MemTest': 1947632SBrad.Beckmann@amd.com exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 1957544SBrad.Beckmann@amd.com else: 1967632SBrad.Beckmann@amd.com exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 1976892SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1986892SBrad.Beckmann@amd.com 1997566SBrad.Beckmann@amd.com if options.recycle_latency: 2007566SBrad.Beckmann@amd.com dma_cntrl.recycle_latency = options.recycle_latency 2017566SBrad.Beckmann@amd.com 2026892SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 2036892SBrad.Beckmann@amd.com 2046893SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 205