MOESI_hammer.py revision 7561
16892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36892SBrad.Beckmann@amd.com# All rights reserved. 46892SBrad.Beckmann@amd.com# 56892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com# this software without specific prior written permission. 156892SBrad.Beckmann@amd.com# 166892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296892SBrad.Beckmann@amd.com 306892SBrad.Beckmann@amd.comimport m5 316892SBrad.Beckmann@amd.comfrom m5.objects import * 326892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 336892SBrad.Beckmann@amd.com 346892SBrad.Beckmann@amd.com# 356892SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 366892SBrad.Beckmann@amd.com# 376892SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 387551SBrad.Beckmann@amd.com latency = 2 396892SBrad.Beckmann@amd.com 406892SBrad.Beckmann@amd.com# 416892SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 426892SBrad.Beckmann@amd.com# 436892SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 447551SBrad.Beckmann@amd.com latency = 10 456892SBrad.Beckmann@amd.com 467538SBrad.Beckmann@amd.comdef define_options(parser): 477561SBrad.Beckmann@amd.com parser.add_option("--allow-atomic-migration", action="store_true", 487561SBrad.Beckmann@amd.com help="allow migratory sharing for atomic only accessed blocks") 497538SBrad.Beckmann@amd.com 507541SBrad.Beckmann@amd.comdef create_system(options, system, piobus, dma_devices): 516892SBrad.Beckmann@amd.com 526892SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_hammer': 536892SBrad.Beckmann@amd.com panic("This script requires the MOESI_hammer protocol to be built.") 546892SBrad.Beckmann@amd.com 556893SBrad.Beckmann@amd.com cpu_sequencers = [] 566893SBrad.Beckmann@amd.com 576892SBrad.Beckmann@amd.com # 586892SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 596892SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 606892SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 616892SBrad.Beckmann@amd.com # 626892SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 636892SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 646892SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 656892SBrad.Beckmann@amd.com 666892SBrad.Beckmann@amd.com # 676892SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 686892SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 696892SBrad.Beckmann@amd.com # 706893SBrad.Beckmann@amd.com 716893SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 726892SBrad.Beckmann@amd.com # 736892SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 746892SBrad.Beckmann@amd.com # 756903SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 766903SBrad.Beckmann@amd.com assoc = options.l1i_assoc) 776903SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 786903SBrad.Beckmann@amd.com assoc = options.l1d_assoc) 796903SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 806903SBrad.Beckmann@amd.com assoc = options.l2_assoc) 816892SBrad.Beckmann@amd.com 827015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 837015SBrad.Beckmann@amd.com icache = l1i_cache, 846892SBrad.Beckmann@amd.com dcache = l1d_cache, 857541SBrad.Beckmann@amd.com physMemPort = system.physmem.port, 867541SBrad.Beckmann@amd.com physmem = system.physmem) 876893SBrad.Beckmann@amd.com 886893SBrad.Beckmann@amd.com if piobus != None: 896893SBrad.Beckmann@amd.com cpu_seq.pio_port = piobus.port 906892SBrad.Beckmann@amd.com 916892SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 926892SBrad.Beckmann@amd.com sequencer = cpu_seq, 936892SBrad.Beckmann@amd.com L1IcacheMemory = l1i_cache, 946892SBrad.Beckmann@amd.com L1DcacheMemory = l1d_cache, 957561SBrad.Beckmann@amd.com L2cacheMemory = l2_cache, 967561SBrad.Beckmann@amd.com no_mig_atomic = not \ 977561SBrad.Beckmann@amd.com options.allow_atomic_migration) 987541SBrad.Beckmann@amd.com 997541SBrad.Beckmann@amd.com exec("system.l1_cntrl%d = l1_cntrl" % i) 1006893SBrad.Beckmann@amd.com # 1016893SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1026893SBrad.Beckmann@amd.com # 1036893SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1046893SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1056893SBrad.Beckmann@amd.com 1067541SBrad.Beckmann@amd.com phys_mem_size = long(system.physmem.range.second) - \ 1077541SBrad.Beckmann@amd.com long(system.physmem.range.first) + 1 1086905SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1096905SBrad.Beckmann@amd.com 1106893SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1116893SBrad.Beckmann@amd.com # 1126893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1136893SBrad.Beckmann@amd.com # 1146892SBrad.Beckmann@amd.com 1156892SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 1166892SBrad.Beckmann@amd.com 1176905SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1186905SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1196905SBrad.Beckmann@amd.com 1206892SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1216893SBrad.Beckmann@amd.com directory = \ 1227541SBrad.Beckmann@amd.com RubyDirectoryMemory( \ 1237541SBrad.Beckmann@amd.com version = i, 1247541SBrad.Beckmann@amd.com size = dir_size, 1257541SBrad.Beckmann@amd.com use_map = options.use_map, 1267541SBrad.Beckmann@amd.com map_levels = \ 1277541SBrad.Beckmann@amd.com options.map_levels), 1286892SBrad.Beckmann@amd.com memBuffer = mem_cntrl) 1296892SBrad.Beckmann@amd.com 1307541SBrad.Beckmann@amd.com exec("system.dir_cntrl%d = dir_cntrl" % i) 1316893SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1326893SBrad.Beckmann@amd.com 1336893SBrad.Beckmann@amd.com for i, dma_device in enumerate(dma_devices): 1346893SBrad.Beckmann@amd.com # 1356893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1366893SBrad.Beckmann@amd.com # 1376893SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1387541SBrad.Beckmann@amd.com physMemPort = system.physmem.port, 1397541SBrad.Beckmann@amd.com physmem = system.physmem) 1406893SBrad.Beckmann@amd.com 1416892SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1426893SBrad.Beckmann@amd.com dma_sequencer = dma_seq) 1436892SBrad.Beckmann@amd.com 1447541SBrad.Beckmann@amd.com exec("system.dma_cntrl%d = dma_cntrl" % i) 1457544SBrad.Beckmann@amd.com if dma_device.type == 'MemTest': 1467544SBrad.Beckmann@amd.com system.dma_cntrl.dma_sequencer.port = dma_device.test 1477544SBrad.Beckmann@amd.com else: 1487544SBrad.Beckmann@amd.com system.dma_cntrl.dma_sequencer.port = dma_device.dma 1496893SBrad.Beckmann@amd.com dma_cntrl.dma_sequencer.port = dma_device.dma 1506892SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1516892SBrad.Beckmann@amd.com 1526892SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1536892SBrad.Beckmann@amd.com 1546893SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 155