MOESI_hammer.py revision 6903
16892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36892SBrad.Beckmann@amd.com# All rights reserved. 46892SBrad.Beckmann@amd.com# 56892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com# this software without specific prior written permission. 156892SBrad.Beckmann@amd.com# 166892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296892SBrad.Beckmann@amd.com 306892SBrad.Beckmann@amd.comimport m5 316892SBrad.Beckmann@amd.comfrom m5.objects import * 326892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 336892SBrad.Beckmann@amd.comfrom m5.util import addToPath 346892SBrad.Beckmann@amd.com 356892SBrad.Beckmann@amd.com 366892SBrad.Beckmann@amd.com# 376892SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 386892SBrad.Beckmann@amd.com# 396892SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 406892SBrad.Beckmann@amd.com latency = 3 416892SBrad.Beckmann@amd.com 426892SBrad.Beckmann@amd.com# 436892SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 446892SBrad.Beckmann@amd.com# 456892SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 466892SBrad.Beckmann@amd.com latency = 15 476892SBrad.Beckmann@amd.com 486893SBrad.Beckmann@amd.comdef create_system(options, phys_mem, piobus, dma_devices): 496892SBrad.Beckmann@amd.com 506892SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_hammer': 516892SBrad.Beckmann@amd.com panic("This script requires the MOESI_hammer protocol to be built.") 526892SBrad.Beckmann@amd.com 536893SBrad.Beckmann@amd.com cpu_sequencers = [] 546893SBrad.Beckmann@amd.com 556892SBrad.Beckmann@amd.com # 566892SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 576892SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 586892SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 596892SBrad.Beckmann@amd.com # 606892SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 616892SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 626892SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 636892SBrad.Beckmann@amd.com 646892SBrad.Beckmann@amd.com # 656892SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 666892SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 676892SBrad.Beckmann@amd.com # 686893SBrad.Beckmann@amd.com 696893SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 706892SBrad.Beckmann@amd.com # 716892SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 726892SBrad.Beckmann@amd.com # 736903SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 746903SBrad.Beckmann@amd.com assoc = options.l1i_assoc) 756903SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 766903SBrad.Beckmann@amd.com assoc = options.l1d_assoc) 776903SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 786903SBrad.Beckmann@amd.com assoc = options.l2_assoc) 796892SBrad.Beckmann@amd.com 806892SBrad.Beckmann@amd.com cpu_seq = RubySequencer(icache = l1i_cache, 816892SBrad.Beckmann@amd.com dcache = l1d_cache, 826893SBrad.Beckmann@amd.com physMemPort = phys_mem.port, 836893SBrad.Beckmann@amd.com physmem = phys_mem) 846893SBrad.Beckmann@amd.com 856893SBrad.Beckmann@amd.com if piobus != None: 866893SBrad.Beckmann@amd.com cpu_seq.pio_port = piobus.port 876892SBrad.Beckmann@amd.com 886892SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 896892SBrad.Beckmann@amd.com sequencer = cpu_seq, 906892SBrad.Beckmann@amd.com L1IcacheMemory = l1i_cache, 916892SBrad.Beckmann@amd.com L1DcacheMemory = l1d_cache, 926892SBrad.Beckmann@amd.com L2cacheMemory = l2_cache) 936893SBrad.Beckmann@amd.com # 946893SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 956893SBrad.Beckmann@amd.com # 966893SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 976893SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 986893SBrad.Beckmann@amd.com 996893SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1006893SBrad.Beckmann@amd.com # 1016893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1026893SBrad.Beckmann@amd.com # 1036892SBrad.Beckmann@amd.com 1046892SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 1056892SBrad.Beckmann@amd.com 1066892SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1076893SBrad.Beckmann@amd.com directory = \ 1086893SBrad.Beckmann@amd.com RubyDirectoryMemory(version = i), 1096892SBrad.Beckmann@amd.com memBuffer = mem_cntrl) 1106892SBrad.Beckmann@amd.com 1116893SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1126893SBrad.Beckmann@amd.com 1136893SBrad.Beckmann@amd.com for i, dma_device in enumerate(dma_devices): 1146893SBrad.Beckmann@amd.com # 1156893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1166893SBrad.Beckmann@amd.com # 1176893SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1186893SBrad.Beckmann@amd.com physMemPort = phys_mem.port, 1196893SBrad.Beckmann@amd.com physmem = phys_mem) 1206893SBrad.Beckmann@amd.com 1216892SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1226893SBrad.Beckmann@amd.com dma_sequencer = dma_seq) 1236892SBrad.Beckmann@amd.com 1246893SBrad.Beckmann@amd.com dma_cntrl.dma_sequencer.port = dma_device.dma 1256892SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1266892SBrad.Beckmann@amd.com 1276892SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1286892SBrad.Beckmann@amd.com 1296893SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 130