MOESI_hammer.py revision 6892
16892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36892SBrad.Beckmann@amd.com# All rights reserved. 46892SBrad.Beckmann@amd.com# 56892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com# this software without specific prior written permission. 156892SBrad.Beckmann@amd.com# 166892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296892SBrad.Beckmann@amd.com 306892SBrad.Beckmann@amd.comimport m5 316892SBrad.Beckmann@amd.comfrom m5.objects import * 326892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 336892SBrad.Beckmann@amd.comfrom m5.util import addToPath 346892SBrad.Beckmann@amd.com 356892SBrad.Beckmann@amd.com 366892SBrad.Beckmann@amd.com# 376892SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 386892SBrad.Beckmann@amd.com# 396892SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 406892SBrad.Beckmann@amd.com assoc = 2 416892SBrad.Beckmann@amd.com latency = 3 426892SBrad.Beckmann@amd.com size = 32768 436892SBrad.Beckmann@amd.com 446892SBrad.Beckmann@amd.com# 456892SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 466892SBrad.Beckmann@amd.com# 476892SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 486892SBrad.Beckmann@amd.com assoc = 16 496892SBrad.Beckmann@amd.com latency = 15 506892SBrad.Beckmann@amd.com size = 1048576 516892SBrad.Beckmann@amd.com 526892SBrad.Beckmann@amd.comdef create_system(options, physmem): 536892SBrad.Beckmann@amd.com 546892SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_hammer': 556892SBrad.Beckmann@amd.com panic("This script requires the MOESI_hammer protocol to be built.") 566892SBrad.Beckmann@amd.com 576892SBrad.Beckmann@amd.com sequencers = [] 586892SBrad.Beckmann@amd.com # 596892SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 606892SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 616892SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 626892SBrad.Beckmann@amd.com # 636892SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 646892SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 656892SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 666892SBrad.Beckmann@amd.com 676892SBrad.Beckmann@amd.com # 686892SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 696892SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 706892SBrad.Beckmann@amd.com # 716892SBrad.Beckmann@amd.com for i in range(options.num_cpus): 726892SBrad.Beckmann@amd.com # 736892SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 746892SBrad.Beckmann@amd.com # Eventually this code should go in a python file specific to the 756892SBrad.Beckmann@amd.com # MOESI_hammer protocol 766892SBrad.Beckmann@amd.com # 776892SBrad.Beckmann@amd.com l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i)) 786892SBrad.Beckmann@amd.com l1i_cache = L1Cache(cache_profiler = l1i_profiler) 796892SBrad.Beckmann@amd.com 806892SBrad.Beckmann@amd.com l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i)) 816892SBrad.Beckmann@amd.com l1d_cache = L1Cache(cache_profiler = l1d_profiler) 826892SBrad.Beckmann@amd.com 836892SBrad.Beckmann@amd.com l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i)) 846892SBrad.Beckmann@amd.com l2_cache = L2Cache(cache_profiler = l2_profiler) 856892SBrad.Beckmann@amd.com 866892SBrad.Beckmann@amd.com cpu_seq = RubySequencer(icache = l1i_cache, 876892SBrad.Beckmann@amd.com dcache = l1d_cache, 886892SBrad.Beckmann@amd.com funcmem_port = physmem.port) 896892SBrad.Beckmann@amd.com 906892SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 916892SBrad.Beckmann@amd.com sequencer = cpu_seq, 926892SBrad.Beckmann@amd.com L1IcacheMemory = l1i_cache, 936892SBrad.Beckmann@amd.com L1DcacheMemory = l1d_cache, 946892SBrad.Beckmann@amd.com L2cacheMemory = l2_cache) 956892SBrad.Beckmann@amd.com 966892SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 976892SBrad.Beckmann@amd.com 986892SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 996892SBrad.Beckmann@amd.com directory = RubyDirectoryMemory(), 1006892SBrad.Beckmann@amd.com memBuffer = mem_cntrl) 1016892SBrad.Beckmann@amd.com 1026892SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1036892SBrad.Beckmann@amd.com dma_sequencer = DMASequencer()) 1046892SBrad.Beckmann@amd.com 1056892SBrad.Beckmann@amd.com # 1066892SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1076892SBrad.Beckmann@amd.com # As noted above: Independent list are track to maintain the order of 1086892SBrad.Beckmann@amd.com # nodes/controllers assumed by the ruby network 1096892SBrad.Beckmann@amd.com # 1106892SBrad.Beckmann@amd.com sequencers.append(cpu_seq) 1116892SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1126892SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1136892SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1146892SBrad.Beckmann@amd.com 1156892SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1166892SBrad.Beckmann@amd.com 1176892SBrad.Beckmann@amd.com return (sequencers, dir_cntrl_nodes, all_cntrls) 118