MOESI_hammer.py revision 11019
16892SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26892SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36892SBrad.Beckmann@amd.com# All rights reserved. 46892SBrad.Beckmann@amd.com# 56892SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66892SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76892SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96892SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106892SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116892SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126892SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136892SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146892SBrad.Beckmann@amd.com# this software without specific prior written permission. 156892SBrad.Beckmann@amd.com# 166892SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176892SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186892SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196892SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206892SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216892SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226892SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236892SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246892SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256892SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266892SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276892SBrad.Beckmann@amd.com# 286892SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296892SBrad.Beckmann@amd.com 307564SBrad.Beckmann@amd.comimport math 316892SBrad.Beckmann@amd.comimport m5 326892SBrad.Beckmann@amd.comfrom m5.objects import * 336892SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366892SBrad.Beckmann@amd.com 376892SBrad.Beckmann@amd.com# 3811019Sjthestness@gmail.com# Declare caches used by the protocol 396892SBrad.Beckmann@amd.com# 4011019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4111019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 426892SBrad.Beckmann@amd.com# 4311019Sjthestness@gmail.com# Probe filter is a cache 446892SBrad.Beckmann@amd.com# 4511019Sjthestness@gmail.comclass ProbeFilter(RubyCache): pass 467564SBrad.Beckmann@amd.com 477538SBrad.Beckmann@amd.comdef define_options(parser): 487561SBrad.Beckmann@amd.com parser.add_option("--allow-atomic-migration", action="store_true", 497561SBrad.Beckmann@amd.com help="allow migratory sharing for atomic only accessed blocks") 507564SBrad.Beckmann@amd.com parser.add_option("--pf-on", action="store_true", 517564SBrad.Beckmann@amd.com help="Hammer: enable Probe Filter") 527904SBrad.Beckmann@amd.com parser.add_option("--dir-on", action="store_true", 537904SBrad.Beckmann@amd.com help="Hammer: enable Full-bit Directory") 547904SBrad.Beckmann@amd.com 5510519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 568436SBrad.Beckmann@amd.com 576892SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_hammer': 586892SBrad.Beckmann@amd.com panic("This script requires the MOESI_hammer protocol to be built.") 596892SBrad.Beckmann@amd.com 606893SBrad.Beckmann@amd.com cpu_sequencers = [] 6110917Sbrandon.potter@amd.com 626892SBrad.Beckmann@amd.com # 636892SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 646892SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 656892SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 666892SBrad.Beckmann@amd.com # 676892SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 686892SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 696892SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 706892SBrad.Beckmann@amd.com 716892SBrad.Beckmann@amd.com # 726892SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 736892SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 746892SBrad.Beckmann@amd.com # 758180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 768257SBrad.Beckmann@amd.com 776893SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 786892SBrad.Beckmann@amd.com # 796892SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 806892SBrad.Beckmann@amd.com # 816903SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 828180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 838653Snilay@cs.wisc.edu start_index_bit = block_size_bits, 848653Snilay@cs.wisc.edu is_icache = True) 856903SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 868180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 878180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 886903SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 898180SBrad.Beckmann@amd.com assoc = options.l2_assoc, 908180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 916892SBrad.Beckmann@amd.com 928322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 939697Snilay@cs.wisc.edu L1Icache = l1i_cache, 949697Snilay@cs.wisc.edu L1Dcache = l1d_cache, 959697Snilay@cs.wisc.edu L2cache = l2_cache, 968322Ssteve.reinhardt@amd.com no_mig_atomic = not \ 978436SBrad.Beckmann@amd.com options.allow_atomic_migration, 9810529Smorr@cs.wisc.edu send_evictions = send_evicts(options), 999841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 10010300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1018436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1028322Ssteve.reinhardt@amd.com 1037015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 1047015SBrad.Beckmann@amd.com icache = l1i_cache, 1056892SBrad.Beckmann@amd.com dcache = l1d_cache, 10610300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1078436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1086893SBrad.Beckmann@amd.com 1098322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 1107566SBrad.Beckmann@amd.com if options.recycle_latency: 1117566SBrad.Beckmann@amd.com l1_cntrl.recycle_latency = options.recycle_latency 1127566SBrad.Beckmann@amd.com 1139468Smalek.musleh@gmail.com exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 11410311Snilay@cs.wisc.edu 1156893SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1166893SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1176893SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1186893SBrad.Beckmann@amd.com 11910311Snilay@cs.wisc.edu # Connect the L1 controller and the network 12010311Snilay@cs.wisc.edu # Connect the buffers from the controller to network 12110311Snilay@cs.wisc.edu l1_cntrl.requestFromCache = ruby_system.network.slave 12210311Snilay@cs.wisc.edu l1_cntrl.responseFromCache = ruby_system.network.slave 12310311Snilay@cs.wisc.edu l1_cntrl.unblockFromCache = ruby_system.network.slave 12410311Snilay@cs.wisc.edu 12510311Snilay@cs.wisc.edu # Connect the buffers from the network to the controller 12610311Snilay@cs.wisc.edu l1_cntrl.forwardToCache = ruby_system.network.master 12710311Snilay@cs.wisc.edu l1_cntrl.responseToCache = ruby_system.network.master 12810311Snilay@cs.wisc.edu 12910311Snilay@cs.wisc.edu 1309826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1319798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1326905SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1336905SBrad.Beckmann@amd.com 1347564SBrad.Beckmann@amd.com # 1357564SBrad.Beckmann@amd.com # determine size and index bits for probe filter 1367564SBrad.Beckmann@amd.com # By default, the probe filter size is configured to be twice the 1377564SBrad.Beckmann@amd.com # size of the L2 cache. 1387564SBrad.Beckmann@amd.com # 1397564SBrad.Beckmann@amd.com pf_size = MemorySize(options.l2_size) 1407564SBrad.Beckmann@amd.com pf_size.value = pf_size.value * 2 1417564SBrad.Beckmann@amd.com dir_bits = int(math.log(options.num_dirs, 2)) 1427564SBrad.Beckmann@amd.com pf_bits = int(math.log(pf_size.value, 2)) 1437564SBrad.Beckmann@amd.com if options.numa_high_bit: 1449318Spower.jg@gmail.com if options.pf_on or options.dir_on: 1457564SBrad.Beckmann@amd.com # if numa high bit explicitly set, make sure it does not overlap 1467564SBrad.Beckmann@amd.com # with the probe filter index 1477564SBrad.Beckmann@amd.com assert(options.numa_high_bit - dir_bits > pf_bits) 1487564SBrad.Beckmann@amd.com 1497564SBrad.Beckmann@amd.com # set the probe filter start bit to just above the block offset 1509318Spower.jg@gmail.com pf_start_bit = block_size_bits 1517564SBrad.Beckmann@amd.com else: 1527564SBrad.Beckmann@amd.com if dir_bits > 0: 1539318Spower.jg@gmail.com pf_start_bit = dir_bits + block_size_bits - 1 1547564SBrad.Beckmann@amd.com else: 1559318Spower.jg@gmail.com pf_start_bit = block_size_bits 1567564SBrad.Beckmann@amd.com 1579793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1589793Sakash.bagdia@arm.com # the ruby system 1599793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1609793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1619793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1629793Sakash.bagdia@arm.com clk_divider=3) 1639793Sakash.bagdia@arm.com 1646893SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1656905SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1666905SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1676905SBrad.Beckmann@amd.com 1687662SBrad.Beckmann@amd.com pf = ProbeFilter(size = pf_size, assoc = 4, 1697662SBrad.Beckmann@amd.com start_index_bit = pf_start_bit) 1707564SBrad.Beckmann@amd.com 1716892SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 17210524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 17310524Snilay@cs.wisc.edu version = i, size = dir_size), 1747564SBrad.Beckmann@amd.com probeFilter = pf, 1757904SBrad.Beckmann@amd.com probe_filter_enabled = options.pf_on, 1768436SBrad.Beckmann@amd.com full_bit_dir_enabled = options.dir_on, 1779841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1788436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1796892SBrad.Beckmann@amd.com 1807566SBrad.Beckmann@amd.com if options.recycle_latency: 1817566SBrad.Beckmann@amd.com dir_cntrl.recycle_latency = options.recycle_latency 1827566SBrad.Beckmann@amd.com 1839468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1846893SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1856893SBrad.Beckmann@amd.com 18610311Snilay@cs.wisc.edu # Connect the directory controller to the network 18710311Snilay@cs.wisc.edu dir_cntrl.forwardFromDir = ruby_system.network.slave 18810311Snilay@cs.wisc.edu dir_cntrl.responseFromDir = ruby_system.network.slave 18910311Snilay@cs.wisc.edu dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 19010311Snilay@cs.wisc.edu 19110311Snilay@cs.wisc.edu dir_cntrl.unblockToDir = ruby_system.network.master 19210311Snilay@cs.wisc.edu dir_cntrl.responseToDir = ruby_system.network.master 19310311Snilay@cs.wisc.edu dir_cntrl.requestToDir = ruby_system.network.master 19410311Snilay@cs.wisc.edu dir_cntrl.dmaRequestToDir = ruby_system.network.master 19510311Snilay@cs.wisc.edu 19610311Snilay@cs.wisc.edu 1978929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1986893SBrad.Beckmann@amd.com # 1996893SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 2006893SBrad.Beckmann@amd.com # 2016893SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 20210519Snilay@cs.wisc.edu ruby_system = ruby_system, 20310519Snilay@cs.wisc.edu slave = dma_port) 20410917Sbrandon.potter@amd.com 2056892SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 2068477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 2079841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 2088477Snilay@cs.wisc.edu ruby_system = ruby_system) 2096892SBrad.Beckmann@amd.com 2109468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 2116892SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 2126892SBrad.Beckmann@amd.com 2137566SBrad.Beckmann@amd.com if options.recycle_latency: 2147566SBrad.Beckmann@amd.com dma_cntrl.recycle_latency = options.recycle_latency 2157566SBrad.Beckmann@amd.com 21610311Snilay@cs.wisc.edu # Connect the dma controller to the network 21710440Snilay@cs.wisc.edu dma_cntrl.responseFromDir = ruby_system.network.master 21810440Snilay@cs.wisc.edu dma_cntrl.requestToDir = ruby_system.network.slave 21910311Snilay@cs.wisc.edu 22010519Snilay@cs.wisc.edu all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 22110311Snilay@cs.wisc.edu 22210519Snilay@cs.wisc.edu # Create the io controller and the sequencer 22310519Snilay@cs.wisc.edu if full_system: 22410519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 22510519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 22610519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 22710519Snilay@cs.wisc.edu dma_sequencer = io_seq, 22810519Snilay@cs.wisc.edu ruby_system = ruby_system) 22910519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 23010519Snilay@cs.wisc.edu 23110519Snilay@cs.wisc.edu # Connect the dma controller to the network 23210519Snilay@cs.wisc.edu io_controller.responseFromDir = ruby_system.network.master 23310519Snilay@cs.wisc.edu io_controller.requestToDir = ruby_system.network.slave 23410519Snilay@cs.wisc.edu 23510519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 23610519Snilay@cs.wisc.edu 2379100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 2389100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 239