MOESI_CMP_token.py revision 9468:721718c62859
12810SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22810SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 32810SN/A# All rights reserved. 42810SN/A# 52810SN/A# Redistribution and use in source and binary forms, with or without 62810SN/A# modification, are permitted provided that the following conditions are 72810SN/A# met: redistributions of source code must retain the above copyright 82810SN/A# notice, this list of conditions and the following disclaimer; 92810SN/A# redistributions in binary form must reproduce the above copyright 102810SN/A# notice, this list of conditions and the following disclaimer in the 112810SN/A# documentation and/or other materials provided with the distribution; 122810SN/A# neither the name of the copyright holders nor the names of its 132810SN/A# contributors may be used to endorse or promote products derived from 142810SN/A# this software without specific prior written permission. 152810SN/A# 162810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A# 282810SN/A# Authors: Brad Beckmann 292810SN/A 302810SN/Aimport math 312810SN/Aimport m5 322810SN/Afrom m5.objects import * 333861SN/Afrom m5.defines import buildEnv 342810SN/Afrom Ruby import create_topology 352810SN/A 3610623Smitch.hayenga@arm.com# 3710623Smitch.hayenga@arm.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 382810SN/A# 3910623Smitch.hayenga@arm.comclass L1Cache(RubyCache): 408831Smrinmoy.ghosh@arm.com latency = 2 418831Smrinmoy.ghosh@arm.com 422810SN/A# 4310623Smitch.hayenga@arm.com# Note: the L2 Cache latency is not currently used 442810SN/A# 4510623Smitch.hayenga@arm.comclass L2Cache(RubyCache): 4610623Smitch.hayenga@arm.com latency = 10 4710623Smitch.hayenga@arm.com 482810SN/Adef define_options(parser): 4910623Smitch.hayenga@arm.com parser.add_option("--l1-retries", type="int", default=1, 502810SN/A help="Token_CMP: # of l1 retries before going persistent") 512810SN/A parser.add_option("--timeout-latency", type="int", default=300, 522810SN/A help="Token_CMP: cycles until issuing again"); 5311439SRekai.GonzalezAlberquilla@arm.com parser.add_option("--disable-dyn-timeouts", action="store_true", 5411439SRekai.GonzalezAlberquilla@arm.com help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 552810SN/A parser.add_option("--allow-atomic-migration", action="store_true", 562810SN/A help="allow migratory sharing for atomic only accessed blocks") 5710623Smitch.hayenga@arm.com 58def create_system(options, system, piobus, dma_ports, ruby_system): 59 60 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 61 panic("This script requires the MOESI_CMP_token protocol to be built.") 62 63 # 64 # number of tokens that the owner passes to requests so that shared blocks can 65 # respond to read requests 66 # 67 n_tokens = options.num_cpus + 1 68 69 cpu_sequencers = [] 70 71 # 72 # The ruby network creation expects the list of nodes in the system to be 73 # consistent with the NetDest list. Therefore the l1 controller nodes must be 74 # listed before the directory nodes and directory nodes before dma nodes, etc. 75 # 76 l1_cntrl_nodes = [] 77 l2_cntrl_nodes = [] 78 dir_cntrl_nodes = [] 79 dma_cntrl_nodes = [] 80 81 # 82 # Must create the individual controllers before the network to ensure the 83 # controller constructors are called before the network constructor 84 # 85 l2_bits = int(math.log(options.num_l2caches, 2)) 86 block_size_bits = int(math.log(options.cacheline_size, 2)) 87 88 cntrl_count = 0 89 90 for i in xrange(options.num_cpus): 91 # 92 # First create the Ruby objects associated with this cpu 93 # 94 l1i_cache = L1Cache(size = options.l1i_size, 95 assoc = options.l1i_assoc, 96 start_index_bit = block_size_bits) 97 l1d_cache = L1Cache(size = options.l1d_size, 98 assoc = options.l1d_assoc, 99 start_index_bit = block_size_bits) 100 101 l1_cntrl = L1Cache_Controller(version = i, 102 cntrl_id = cntrl_count, 103 L1IcacheMemory = l1i_cache, 104 L1DcacheMemory = l1d_cache, 105 l2_select_num_bits = l2_bits, 106 N_tokens = n_tokens, 107 retry_threshold = \ 108 options.l1_retries, 109 fixed_timeout_latency = \ 110 options.timeout_latency, 111 dynamic_timeout_enabled = \ 112 not options.disable_dyn_timeouts, 113 no_mig_atomic = not \ 114 options.allow_atomic_migration, 115 send_evictions = ( 116 options.cpu_type == "detailed"), 117 ruby_system = ruby_system) 118 119 cpu_seq = RubySequencer(version = i, 120 icache = l1i_cache, 121 dcache = l1d_cache, 122 ruby_system = ruby_system) 123 124 l1_cntrl.sequencer = cpu_seq 125 126 if piobus != None: 127 cpu_seq.pio_port = piobus.slave 128 129 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 130 # 131 # Add controllers and sequencers to the appropriate lists 132 # 133 cpu_sequencers.append(cpu_seq) 134 l1_cntrl_nodes.append(l1_cntrl) 135 136 cntrl_count += 1 137 138 l2_index_start = block_size_bits + l2_bits 139 140 for i in xrange(options.num_l2caches): 141 # 142 # First create the Ruby objects associated with this cpu 143 # 144 l2_cache = L2Cache(size = options.l2_size, 145 assoc = options.l2_assoc, 146 start_index_bit = l2_index_start) 147 148 l2_cntrl = L2Cache_Controller(version = i, 149 cntrl_id = cntrl_count, 150 L2cacheMemory = l2_cache, 151 N_tokens = n_tokens, 152 ruby_system = ruby_system) 153 154 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 155 l2_cntrl_nodes.append(l2_cntrl) 156 157 cntrl_count += 1 158 159 phys_mem_size = sum(map(lambda mem: mem.range.size(), 160 system.memories.unproxy(system))) 161 mem_module_size = phys_mem_size / options.num_dirs 162 163 for i in xrange(options.num_dirs): 164 # 165 # Create the Ruby objects associated with the directory controller 166 # 167 168 mem_cntrl = RubyMemoryControl(version = i, 169 ruby_system = ruby_system) 170 171 dir_size = MemorySize('0B') 172 dir_size.value = mem_module_size 173 174 dir_cntrl = Directory_Controller(version = i, 175 cntrl_id = cntrl_count, 176 directory = \ 177 RubyDirectoryMemory(version = i, 178 size = dir_size), 179 memBuffer = mem_cntrl, 180 l2_select_num_bits = l2_bits, 181 ruby_system = ruby_system) 182 183 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 184 dir_cntrl_nodes.append(dir_cntrl) 185 186 cntrl_count += 1 187 188 for i, dma_port in enumerate(dma_ports): 189 # 190 # Create the Ruby objects associated with the dma controller 191 # 192 dma_seq = DMASequencer(version = i, 193 ruby_system = ruby_system) 194 195 dma_cntrl = DMA_Controller(version = i, 196 cntrl_id = cntrl_count, 197 dma_sequencer = dma_seq, 198 ruby_system = ruby_system) 199 200 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 201 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 202 dma_cntrl_nodes.append(dma_cntrl) 203 cntrl_count += 1 204 205 all_cntrls = l1_cntrl_nodes + \ 206 l2_cntrl_nodes + \ 207 dir_cntrl_nodes + \ 208 dma_cntrl_nodes 209 210 topology = create_topology(all_cntrls, options) 211 212 return (cpu_sequencers, dir_cntrl_nodes, topology) 213