MOESI_CMP_token.py revision 8180:d8587c913ccf
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34 35# 36# Note: the L1 Cache latency is only used by the sequencer on fast path hits 37# 38class L1Cache(RubyCache): 39 latency = 2 40 41# 42# Note: the L2 Cache latency is not currently used 43# 44class L2Cache(RubyCache): 45 latency = 10 46 47def define_options(parser): 48 parser.add_option("--l1-retries", type="int", default=1, 49 help="Token_CMP: # of l1 retries before going persistent") 50 parser.add_option("--timeout-latency", type="int", default=300, 51 help="Token_CMP: cycles until issuing again"); 52 parser.add_option("--disable-dyn-timeouts", action="store_true", 53 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 54 parser.add_option("--allow-atomic-migration", action="store_true", 55 help="allow migratory sharing for atomic only accessed blocks") 56 57def create_system(options, system, piobus, dma_devices): 58 59 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 60 panic("This script requires the MOESI_CMP_token protocol to be built.") 61 62 # 63 # number of tokens that the owner passes to requests so that shared blocks can 64 # respond to read requests 65 # 66 n_tokens = options.num_cpus + 1 67 68 cpu_sequencers = [] 69 70 # 71 # The ruby network creation expects the list of nodes in the system to be 72 # consistent with the NetDest list. Therefore the l1 controller nodes must be 73 # listed before the directory nodes and directory nodes before dma nodes, etc. 74 # 75 l1_cntrl_nodes = [] 76 l2_cntrl_nodes = [] 77 dir_cntrl_nodes = [] 78 dma_cntrl_nodes = [] 79 80 # 81 # Must create the individual controllers before the network to ensure the 82 # controller constructors are called before the network constructor 83 # 84 l2_bits = int(math.log(options.num_l2caches, 2)) 85 block_size_bits = int(math.log(options.cacheline_size, 2)) 86 87 for i in xrange(options.num_cpus): 88 # 89 # First create the Ruby objects associated with this cpu 90 # 91 l1i_cache = L1Cache(size = options.l1i_size, 92 assoc = options.l1i_assoc, 93 start_index_bit = block_size_bits) 94 l1d_cache = L1Cache(size = options.l1d_size, 95 assoc = options.l1d_assoc, 96 start_index_bit = block_size_bits) 97 98 cpu_seq = RubySequencer(version = i, 99 icache = l1i_cache, 100 dcache = l1d_cache, 101 physMemPort = system.physmem.port, 102 physmem = system.physmem) 103 104 if piobus != None: 105 cpu_seq.pio_port = piobus.port 106 107 l1_cntrl = L1Cache_Controller(version = i, 108 sequencer = cpu_seq, 109 L1IcacheMemory = l1i_cache, 110 L1DcacheMemory = l1d_cache, 111 l2_select_num_bits = l2_bits, 112 N_tokens = n_tokens, 113 retry_threshold = \ 114 options.l1_retries, 115 fixed_timeout_latency = \ 116 options.timeout_latency, 117 dynamic_timeout_enabled = \ 118 not options.disable_dyn_timeouts, 119 no_mig_atomic = not \ 120 options.allow_atomic_migration) 121 122 exec("system.l1_cntrl%d = l1_cntrl" % i) 123 # 124 # Add controllers and sequencers to the appropriate lists 125 # 126 cpu_sequencers.append(cpu_seq) 127 l1_cntrl_nodes.append(l1_cntrl) 128 129 l2_index_start = block_size_bits + l2_bits 130 131 for i in xrange(options.num_l2caches): 132 # 133 # First create the Ruby objects associated with this cpu 134 # 135 l2_cache = L2Cache(size = options.l2_size, 136 assoc = options.l2_assoc, 137 start_index_bit = l2_index_start) 138 139 l2_cntrl = L2Cache_Controller(version = i, 140 L2cacheMemory = l2_cache, 141 N_tokens = n_tokens) 142 143 exec("system.l2_cntrl%d = l2_cntrl" % i) 144 l2_cntrl_nodes.append(l2_cntrl) 145 146 phys_mem_size = long(system.physmem.range.second) - \ 147 long(system.physmem.range.first) + 1 148 mem_module_size = phys_mem_size / options.num_dirs 149 150 for i in xrange(options.num_dirs): 151 # 152 # Create the Ruby objects associated with the directory controller 153 # 154 155 mem_cntrl = RubyMemoryControl(version = i) 156 157 dir_size = MemorySize('0B') 158 dir_size.value = mem_module_size 159 160 dir_cntrl = Directory_Controller(version = i, 161 directory = \ 162 RubyDirectoryMemory(version = i, 163 size = \ 164 dir_size), 165 memBuffer = mem_cntrl, 166 l2_select_num_bits = l2_bits) 167 168 exec("system.dir_cntrl%d = dir_cntrl" % i) 169 dir_cntrl_nodes.append(dir_cntrl) 170 171 for i, dma_device in enumerate(dma_devices): 172 # 173 # Create the Ruby objects associated with the dma controller 174 # 175 dma_seq = DMASequencer(version = i, 176 physMemPort = system.physmem.port, 177 physmem = system.physmem) 178 179 dma_cntrl = DMA_Controller(version = i, 180 dma_sequencer = dma_seq) 181 182 exec("system.dma_cntrl%d = dma_cntrl" % i) 183 if dma_device.type == 'MemTest': 184 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 185 else: 186 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 187 dma_cntrl_nodes.append(dma_cntrl) 188 189 all_cntrls = l1_cntrl_nodes + \ 190 l2_cntrl_nodes + \ 191 dir_cntrl_nodes + \ 192 dma_cntrl_nodes 193 194 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 195