MOESI_CMP_token.py revision 7538 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39    latency = 3
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45    latency = 15
46
47def define_options(parser):
48    return
49
50def create_system(options, phys_mem, piobus, dma_devices):
51
52    if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
53        panic("This script requires the MOESI_CMP_token protocol to be built.")
54
55    #
56    # number of tokens that the owner passes to requests so that shared blocks can
57    # respond to read requests
58    #
59    n_tokens = options.num_cpus + 1
60
61    cpu_sequencers = []
62
63    #
64    # The ruby network creation expects the list of nodes in the system to be
65    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
66    # listed before the directory nodes and directory nodes before dma nodes, etc.
67    #
68    l1_cntrl_nodes = []
69    l2_cntrl_nodes = []
70    dir_cntrl_nodes = []
71    dma_cntrl_nodes = []
72
73    #
74    # Must create the individual controllers before the network to ensure the
75    # controller constructors are called before the network constructor
76    #
77
78    for i in xrange(options.num_cpus):
79        #
80        # First create the Ruby objects associated with this cpu
81        #
82        l1i_cache = L1Cache(size = options.l1i_size,
83                            assoc = options.l1i_assoc)
84        l1d_cache = L1Cache(size = options.l1d_size,
85                            assoc = options.l1d_assoc)
86
87        cpu_seq = RubySequencer(version = i,
88                                icache = l1i_cache,
89                                dcache = l1d_cache,
90                                physMemPort = phys_mem.port,
91                                physmem = phys_mem)
92
93        if piobus != None:
94            cpu_seq.pio_port = piobus.port
95
96        l1_cntrl = L1Cache_Controller(version = i,
97                                      sequencer = cpu_seq,
98                                      L1IcacheMemory = l1i_cache,
99                                      L1DcacheMemory = l1d_cache,
100                                      l2_select_num_bits = \
101                                        math.log(options.num_l2caches, 2),
102                                      N_tokens = n_tokens)
103        #
104        # Add controllers and sequencers to the appropriate lists
105        #
106        cpu_sequencers.append(cpu_seq)
107        l1_cntrl_nodes.append(l1_cntrl)
108
109    for i in xrange(options.num_l2caches):
110        #
111        # First create the Ruby objects associated with this cpu
112        #
113        l2_cache = L2Cache(size = options.l2_size,
114                           assoc = options.l2_assoc)
115
116        l2_cntrl = L2Cache_Controller(version = i,
117                                      L2cacheMemory = l2_cache,
118                                      N_tokens = n_tokens)
119
120        l2_cntrl_nodes.append(l2_cntrl)
121
122    phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
123    mem_module_size = phys_mem_size / options.num_dirs
124
125    for i in xrange(options.num_dirs):
126        #
127        # Create the Ruby objects associated with the directory controller
128        #
129
130        mem_cntrl = RubyMemoryControl(version = i)
131
132        dir_size = MemorySize('0B')
133        dir_size.value = mem_module_size
134
135        dir_cntrl = Directory_Controller(version = i,
136                                         directory = \
137                                         RubyDirectoryMemory(version = i,
138                                                             size = dir_size),
139                                         memBuffer = mem_cntrl,
140                                         l2_select_num_bits = \
141                                           math.log(options.num_l2caches, 2))
142
143        dir_cntrl_nodes.append(dir_cntrl)
144
145    for i, dma_device in enumerate(dma_devices):
146        #
147        # Create the Ruby objects associated with the dma controller
148        #
149        dma_seq = DMASequencer(version = i,
150                               physMemPort = phys_mem.port,
151                               physmem = phys_mem)
152
153        dma_cntrl = DMA_Controller(version = i,
154                                   dma_sequencer = dma_seq)
155
156        dma_cntrl.dma_sequencer.port = dma_device.dma
157        dma_cntrl_nodes.append(dma_cntrl)
158
159    all_cntrls = l1_cntrl_nodes + \
160                 l2_cntrl_nodes + \
161                 dir_cntrl_nodes + \
162                 dma_cntrl_nodes
163
164    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
165