MOESI_CMP_token.py revision 7032:9f938aea1942
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 latency = 3 41 42# 43# Note: the L2 Cache latency is not currently used 44# 45class L2Cache(RubyCache): 46 latency = 15 47 48def create_system(options, phys_mem, piobus, dma_devices): 49 50 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 51 panic("This script requires the MOESI_CMP_token protocol to be built.") 52 53 # 54 # number of tokens that the owner passes to requests so that shared blocks can 55 # respond to read requests 56 # 57 n_tokens = options.num_cpus + 1 58 59 cpu_sequencers = [] 60 61 # 62 # The ruby network creation expects the list of nodes in the system to be 63 # consistent with the NetDest list. Therefore the l1 controller nodes must be 64 # listed before the directory nodes and directory nodes before dma nodes, etc. 65 # 66 l1_cntrl_nodes = [] 67 l2_cntrl_nodes = [] 68 dir_cntrl_nodes = [] 69 dma_cntrl_nodes = [] 70 71 # 72 # Must create the individual controllers before the network to ensure the 73 # controller constructors are called before the network constructor 74 # 75 76 for i in xrange(options.num_cpus): 77 # 78 # First create the Ruby objects associated with this cpu 79 # 80 l1i_cache = L1Cache(size = options.l1i_size, 81 assoc = options.l1i_assoc) 82 l1d_cache = L1Cache(size = options.l1d_size, 83 assoc = options.l1d_assoc) 84 85 cpu_seq = RubySequencer(version = i, 86 icache = l1i_cache, 87 dcache = l1d_cache, 88 physMemPort = phys_mem.port, 89 physmem = phys_mem) 90 91 if piobus != None: 92 cpu_seq.pio_port = piobus.port 93 94 l1_cntrl = L1Cache_Controller(version = i, 95 sequencer = cpu_seq, 96 L1IcacheMemory = l1i_cache, 97 L1DcacheMemory = l1d_cache, 98 l2_select_num_bits = \ 99 math.log(options.num_l2caches, 2), 100 N_tokens = n_tokens) 101 # 102 # Add controllers and sequencers to the appropriate lists 103 # 104 cpu_sequencers.append(cpu_seq) 105 l1_cntrl_nodes.append(l1_cntrl) 106 107 for i in xrange(options.num_l2caches): 108 # 109 # First create the Ruby objects associated with this cpu 110 # 111 l2_cache = L2Cache(size = options.l2_size, 112 assoc = options.l2_assoc) 113 114 l2_cntrl = L2Cache_Controller(version = i, 115 L2cacheMemory = l2_cache, 116 N_tokens = n_tokens) 117 118 l2_cntrl_nodes.append(l2_cntrl) 119 120 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 121 mem_module_size = phys_mem_size / options.num_dirs 122 123 for i in xrange(options.num_dirs): 124 # 125 # Create the Ruby objects associated with the directory controller 126 # 127 128 mem_cntrl = RubyMemoryControl(version = i) 129 130 dir_size = MemorySize('0B') 131 dir_size.value = mem_module_size 132 133 dir_cntrl = Directory_Controller(version = i, 134 directory = \ 135 RubyDirectoryMemory(version = i, 136 size = dir_size), 137 memBuffer = mem_cntrl, 138 l2_select_num_bits = \ 139 math.log(options.num_l2caches, 2)) 140 141 dir_cntrl_nodes.append(dir_cntrl) 142 143 for i, dma_device in enumerate(dma_devices): 144 # 145 # Create the Ruby objects associated with the dma controller 146 # 147 dma_seq = DMASequencer(version = i, 148 physMemPort = phys_mem.port, 149 physmem = phys_mem) 150 151 dma_cntrl = DMA_Controller(version = i, 152 dma_sequencer = dma_seq) 153 154 dma_cntrl.dma_sequencer.port = dma_device.dma 155 dma_cntrl_nodes.append(dma_cntrl) 156 157 all_cntrls = l1_cntrl_nodes + \ 158 l2_cntrl_nodes + \ 159 dir_cntrl_nodes + \ 160 dma_cntrl_nodes 161 162 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 163