MOESI_CMP_token.py revision 11266:452e10b868ea
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35from Ruby import send_evicts 36 37# 38# Declare caches used by the protocol 39# 40class L1Cache(RubyCache): pass 41class L2Cache(RubyCache): pass 42 43def define_options(parser): 44 parser.add_option("--l1-retries", type="int", default=1, 45 help="Token_CMP: # of l1 retries before going persistent") 46 parser.add_option("--timeout-latency", type="int", default=300, 47 help="Token_CMP: cycles until issuing again"); 48 parser.add_option("--disable-dyn-timeouts", action="store_true", 49 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 50 parser.add_option("--allow-atomic-migration", action="store_true", 51 help="allow migratory sharing for atomic only accessed blocks") 52 53def create_system(options, full_system, system, dma_ports, ruby_system): 54 55 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 56 panic("This script requires the MOESI_CMP_token protocol to be built.") 57 58 # 59 # number of tokens that the owner passes to requests so that shared blocks can 60 # respond to read requests 61 # 62 n_tokens = options.num_cpus + 1 63 64 cpu_sequencers = [] 65 66 # 67 # The ruby network creation expects the list of nodes in the system to be 68 # consistent with the NetDest list. Therefore the l1 controller nodes must be 69 # listed before the directory nodes and directory nodes before dma nodes, etc. 70 # 71 l1_cntrl_nodes = [] 72 l2_cntrl_nodes = [] 73 dir_cntrl_nodes = [] 74 dma_cntrl_nodes = [] 75 76 # 77 # Must create the individual controllers before the network to ensure the 78 # controller constructors are called before the network constructor 79 # 80 l2_bits = int(math.log(options.num_l2caches, 2)) 81 block_size_bits = int(math.log(options.cacheline_size, 2)) 82 83 for i in xrange(options.num_cpus): 84 # 85 # First create the Ruby objects associated with this cpu 86 # 87 l1i_cache = L1Cache(size = options.l1i_size, 88 assoc = options.l1i_assoc, 89 start_index_bit = block_size_bits) 90 l1d_cache = L1Cache(size = options.l1d_size, 91 assoc = options.l1d_assoc, 92 start_index_bit = block_size_bits) 93 94 # the ruby random tester reuses num_cpus to specify the 95 # number of cpu ports connected to the tester object, which 96 # is stored in system.cpu. because there is only ever one 97 # tester object, num_cpus is not necessarily equal to the 98 # size of system.cpu; therefore if len(system.cpu) == 1 99 # we use system.cpu[0] to set the clk_domain, thereby ensuring 100 # we don't index off the end of the cpu list. 101 if len(system.cpu) == 1: 102 clk_domain = system.cpu[0].clk_domain 103 else: 104 clk_domain = system.cpu[i].clk_domain 105 106 l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, 107 L1Dcache=l1d_cache, 108 l2_select_num_bits=l2_bits, 109 N_tokens=n_tokens, 110 retry_threshold=options.l1_retries, 111 fixed_timeout_latency=\ 112 options.timeout_latency, 113 dynamic_timeout_enabled=\ 114 not options.disable_dyn_timeouts, 115 no_mig_atomic=not \ 116 options.allow_atomic_migration, 117 send_evictions=send_evicts(options), 118 transitions_per_cycle=options.ports, 119 clk_domain=clk_domain, 120 ruby_system=ruby_system) 121 122 cpu_seq = RubySequencer(version=i, icache=l1i_cache, 123 dcache=l1d_cache, clk_domain=clk_domain, 124 ruby_system=ruby_system) 125 126 l1_cntrl.sequencer = cpu_seq 127 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 128 129 # Add controllers and sequencers to the appropriate lists 130 cpu_sequencers.append(cpu_seq) 131 l1_cntrl_nodes.append(l1_cntrl) 132 133 # Connect the L1 controllers and the network 134 l1_cntrl.requestFromL1Cache = MessageBuffer() 135 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 136 l1_cntrl.responseFromL1Cache = MessageBuffer() 137 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 138 l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True) 139 l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave 140 141 l1_cntrl.mandatoryQueue = MessageBuffer() 142 l1_cntrl.requestToL1Cache = MessageBuffer() 143 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 144 l1_cntrl.responseToL1Cache = MessageBuffer() 145 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 146 l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True) 147 l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master 148 149 150 l2_index_start = block_size_bits + l2_bits 151 152 for i in xrange(options.num_l2caches): 153 # 154 # First create the Ruby objects associated with this cpu 155 # 156 l2_cache = L2Cache(size = options.l2_size, 157 assoc = options.l2_assoc, 158 start_index_bit = l2_index_start) 159 160 l2_cntrl = L2Cache_Controller(version = i, 161 L2cache = l2_cache, 162 N_tokens = n_tokens, 163 transitions_per_cycle = options.ports, 164 ruby_system = ruby_system) 165 166 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 167 l2_cntrl_nodes.append(l2_cntrl) 168 169 # Connect the L2 controllers and the network 170 l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() 171 l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave 172 l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 173 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 174 l2_cntrl.responseFromL2Cache = MessageBuffer() 175 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 176 177 l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() 178 l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master 179 l2_cntrl.L1RequestToL2Cache = MessageBuffer() 180 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 181 l2_cntrl.responseToL2Cache = MessageBuffer() 182 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 183 l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True) 184 l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master 185 186 187 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 188 assert(phys_mem_size % options.num_dirs == 0) 189 mem_module_size = phys_mem_size / options.num_dirs 190 191 # Run each of the ruby memory controllers at a ratio of the frequency of 192 # the ruby system 193 # clk_divider value is a fix to pass regression. 194 ruby_system.memctrl_clk_domain = DerivedClockDomain( 195 clk_domain=ruby_system.clk_domain, 196 clk_divider=3) 197 198 for i in xrange(options.num_dirs): 199 dir_size = MemorySize('0B') 200 dir_size.value = mem_module_size 201 202 dir_cntrl = Directory_Controller(version = i, 203 directory = RubyDirectoryMemory( 204 version = i, size = dir_size), 205 l2_select_num_bits = l2_bits, 206 transitions_per_cycle = options.ports, 207 ruby_system = ruby_system) 208 209 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 210 dir_cntrl_nodes.append(dir_cntrl) 211 212 # Connect the directory controllers and the network 213 dir_cntrl.requestToDir = MessageBuffer() 214 dir_cntrl.requestToDir.slave = ruby_system.network.master 215 dir_cntrl.responseToDir = MessageBuffer() 216 dir_cntrl.responseToDir.slave = ruby_system.network.master 217 dir_cntrl.persistentToDir = MessageBuffer(ordered = True) 218 dir_cntrl.persistentToDir.slave = ruby_system.network.master 219 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) 220 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master 221 222 dir_cntrl.requestFromDir = MessageBuffer() 223 dir_cntrl.requestFromDir.master = ruby_system.network.slave 224 dir_cntrl.responseFromDir = MessageBuffer() 225 dir_cntrl.responseFromDir.master = ruby_system.network.slave 226 dir_cntrl.persistentFromDir = MessageBuffer(ordered = True) 227 dir_cntrl.persistentFromDir.master = ruby_system.network.slave 228 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) 229 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave 230 dir_cntrl.responseFromMemory = MessageBuffer() 231 232 233 for i, dma_port in enumerate(dma_ports): 234 # 235 # Create the Ruby objects associated with the dma controller 236 # 237 dma_seq = DMASequencer(version = i, 238 ruby_system = ruby_system, 239 slave = dma_port) 240 241 dma_cntrl = DMA_Controller(version = i, 242 dma_sequencer = dma_seq, 243 transitions_per_cycle = options.ports, 244 ruby_system = ruby_system) 245 246 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 247 dma_cntrl_nodes.append(dma_cntrl) 248 249 # Connect the dma controller to the network 250 dma_cntrl.mandatoryQueue = MessageBuffer() 251 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 252 dma_cntrl.responseFromDir.slave = ruby_system.network.master 253 dma_cntrl.reqToDirectory = MessageBuffer() 254 dma_cntrl.reqToDirectory.master = ruby_system.network.slave 255 256 all_cntrls = l1_cntrl_nodes + \ 257 l2_cntrl_nodes + \ 258 dir_cntrl_nodes + \ 259 dma_cntrl_nodes 260 261 # Create the io controller and the sequencer 262 if full_system: 263 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 264 ruby_system._io_port = io_seq 265 io_controller = DMA_Controller(version = len(dma_ports), 266 dma_sequencer = io_seq, 267 ruby_system = ruby_system) 268 ruby_system.io_controller = io_controller 269 270 # Connect the dma controller to the network 271 io_controller.mandatoryQueue = MessageBuffer() 272 io_controller.responseFromDir = MessageBuffer(ordered = True) 273 io_controller.responseFromDir.slave = ruby_system.network.master 274 io_controller.reqToDirectory = MessageBuffer() 275 io_controller.reqToDirectory.master = ruby_system.network.slave 276 277 all_cntrls = all_cntrls + [io_controller] 278 279 280 ruby_system.network.number_of_virtual_networks = 6 281 topology = create_topology(all_cntrls, options) 282 return (cpu_sequencers, dir_cntrl_nodes, topology) 283