MOESI_CMP_token.py revision 11022:e6e3b7097810
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35from Ruby import send_evicts 36 37# 38# Declare caches used by the protocol 39# 40class L1Cache(RubyCache): pass 41class L2Cache(RubyCache): pass 42 43def define_options(parser): 44 parser.add_option("--l1-retries", type="int", default=1, 45 help="Token_CMP: # of l1 retries before going persistent") 46 parser.add_option("--timeout-latency", type="int", default=300, 47 help="Token_CMP: cycles until issuing again"); 48 parser.add_option("--disable-dyn-timeouts", action="store_true", 49 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 50 parser.add_option("--allow-atomic-migration", action="store_true", 51 help="allow migratory sharing for atomic only accessed blocks") 52 53def create_system(options, full_system, system, dma_ports, ruby_system): 54 55 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 56 panic("This script requires the MOESI_CMP_token protocol to be built.") 57 58 # 59 # number of tokens that the owner passes to requests so that shared blocks can 60 # respond to read requests 61 # 62 n_tokens = options.num_cpus + 1 63 64 cpu_sequencers = [] 65 66 # 67 # The ruby network creation expects the list of nodes in the system to be 68 # consistent with the NetDest list. Therefore the l1 controller nodes must be 69 # listed before the directory nodes and directory nodes before dma nodes, etc. 70 # 71 l1_cntrl_nodes = [] 72 l2_cntrl_nodes = [] 73 dir_cntrl_nodes = [] 74 dma_cntrl_nodes = [] 75 76 # 77 # Must create the individual controllers before the network to ensure the 78 # controller constructors are called before the network constructor 79 # 80 l2_bits = int(math.log(options.num_l2caches, 2)) 81 block_size_bits = int(math.log(options.cacheline_size, 2)) 82 83 for i in xrange(options.num_cpus): 84 # 85 # First create the Ruby objects associated with this cpu 86 # 87 l1i_cache = L1Cache(size = options.l1i_size, 88 assoc = options.l1i_assoc, 89 start_index_bit = block_size_bits) 90 l1d_cache = L1Cache(size = options.l1d_size, 91 assoc = options.l1d_assoc, 92 start_index_bit = block_size_bits) 93 94 l1_cntrl = L1Cache_Controller(version = i, 95 L1Icache = l1i_cache, 96 L1Dcache = l1d_cache, 97 l2_select_num_bits = l2_bits, 98 N_tokens = n_tokens, 99 retry_threshold = \ 100 options.l1_retries, 101 fixed_timeout_latency = \ 102 options.timeout_latency, 103 dynamic_timeout_enabled = \ 104 not options.disable_dyn_timeouts, 105 no_mig_atomic = not \ 106 options.allow_atomic_migration, 107 send_evictions = send_evicts(options), 108 transitions_per_cycle = options.ports, 109 clk_domain=system.cpu[i].clk_domain, 110 ruby_system = ruby_system) 111 112 cpu_seq = RubySequencer(version = i, 113 icache = l1i_cache, 114 dcache = l1d_cache, 115 clk_domain=system.cpu[i].clk_domain, 116 ruby_system = ruby_system) 117 118 l1_cntrl.sequencer = cpu_seq 119 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 120 121 # Add controllers and sequencers to the appropriate lists 122 cpu_sequencers.append(cpu_seq) 123 l1_cntrl_nodes.append(l1_cntrl) 124 125 # Connect the L1 controllers and the network 126 l1_cntrl.requestFromL1Cache = MessageBuffer() 127 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 128 l1_cntrl.responseFromL1Cache = MessageBuffer() 129 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 130 l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True) 131 l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave 132 133 l1_cntrl.mandatoryQueue = MessageBuffer() 134 l1_cntrl.requestToL1Cache = MessageBuffer() 135 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 136 l1_cntrl.responseToL1Cache = MessageBuffer() 137 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 138 l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True) 139 l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master 140 141 142 l2_index_start = block_size_bits + l2_bits 143 144 for i in xrange(options.num_l2caches): 145 # 146 # First create the Ruby objects associated with this cpu 147 # 148 l2_cache = L2Cache(size = options.l2_size, 149 assoc = options.l2_assoc, 150 start_index_bit = l2_index_start) 151 152 l2_cntrl = L2Cache_Controller(version = i, 153 L2cache = l2_cache, 154 N_tokens = n_tokens, 155 transitions_per_cycle = options.ports, 156 ruby_system = ruby_system) 157 158 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 159 l2_cntrl_nodes.append(l2_cntrl) 160 161 # Connect the L2 controllers and the network 162 l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() 163 l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave 164 l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 165 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 166 l2_cntrl.responseFromL2Cache = MessageBuffer() 167 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 168 169 l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() 170 l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master 171 l2_cntrl.L1RequestToL2Cache = MessageBuffer() 172 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 173 l2_cntrl.responseToL2Cache = MessageBuffer() 174 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 175 l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True) 176 l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master 177 178 179 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 180 assert(phys_mem_size % options.num_dirs == 0) 181 mem_module_size = phys_mem_size / options.num_dirs 182 183 # Run each of the ruby memory controllers at a ratio of the frequency of 184 # the ruby system 185 # clk_divider value is a fix to pass regression. 186 ruby_system.memctrl_clk_domain = DerivedClockDomain( 187 clk_domain=ruby_system.clk_domain, 188 clk_divider=3) 189 190 for i in xrange(options.num_dirs): 191 dir_size = MemorySize('0B') 192 dir_size.value = mem_module_size 193 194 dir_cntrl = Directory_Controller(version = i, 195 directory = RubyDirectoryMemory( 196 version = i, size = dir_size), 197 l2_select_num_bits = l2_bits, 198 transitions_per_cycle = options.ports, 199 ruby_system = ruby_system) 200 201 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 202 dir_cntrl_nodes.append(dir_cntrl) 203 204 # Connect the directory controllers and the network 205 dir_cntrl.requestToDir = MessageBuffer() 206 dir_cntrl.requestToDir.slave = ruby_system.network.master 207 dir_cntrl.responseToDir = MessageBuffer() 208 dir_cntrl.responseToDir.slave = ruby_system.network.master 209 dir_cntrl.persistentToDir = MessageBuffer(ordered = True) 210 dir_cntrl.persistentToDir.slave = ruby_system.network.master 211 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) 212 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master 213 214 dir_cntrl.requestFromDir = MessageBuffer() 215 dir_cntrl.requestFromDir.master = ruby_system.network.slave 216 dir_cntrl.responseFromDir = MessageBuffer() 217 dir_cntrl.responseFromDir.master = ruby_system.network.slave 218 dir_cntrl.persistentFromDir = MessageBuffer(ordered = True) 219 dir_cntrl.persistentFromDir.master = ruby_system.network.slave 220 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) 221 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave 222 dir_cntrl.responseFromMemory = MessageBuffer() 223 224 225 for i, dma_port in enumerate(dma_ports): 226 # 227 # Create the Ruby objects associated with the dma controller 228 # 229 dma_seq = DMASequencer(version = i, 230 ruby_system = ruby_system, 231 slave = dma_port) 232 233 dma_cntrl = DMA_Controller(version = i, 234 dma_sequencer = dma_seq, 235 transitions_per_cycle = options.ports, 236 ruby_system = ruby_system) 237 238 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 239 dma_cntrl_nodes.append(dma_cntrl) 240 241 # Connect the dma controller to the network 242 dma_cntrl.mandatoryQueue = MessageBuffer() 243 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 244 dma_cntrl.responseFromDir.slave = ruby_system.network.master 245 dma_cntrl.reqToDirectory = MessageBuffer() 246 dma_cntrl.reqToDirectory.master = ruby_system.network.slave 247 248 all_cntrls = l1_cntrl_nodes + \ 249 l2_cntrl_nodes + \ 250 dir_cntrl_nodes + \ 251 dma_cntrl_nodes 252 253 # Create the io controller and the sequencer 254 if full_system: 255 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 256 ruby_system._io_port = io_seq 257 io_controller = DMA_Controller(version = len(dma_ports), 258 dma_sequencer = io_seq, 259 ruby_system = ruby_system) 260 ruby_system.io_controller = io_controller 261 262 # Connect the dma controller to the network 263 io_controller.mandatoryQueue = MessageBuffer() 264 io_controller.responseFromDir = MessageBuffer(ordered = True) 265 io_controller.responseFromDir.slave = ruby_system.network.master 266 io_controller.reqToDirectory = MessageBuffer() 267 io_controller.reqToDirectory.master = ruby_system.network.slave 268 269 all_cntrls = all_cntrls + [io_controller] 270 271 272 topology = create_topology(all_cntrls, options) 273 return (cpu_sequencers, dir_cntrl_nodes, topology) 274