MOESI_CMP_token.py revision 11019
16908SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26908SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36908SBrad.Beckmann@amd.com# All rights reserved. 46908SBrad.Beckmann@amd.com# 56908SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66908SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76908SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86908SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96908SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106908SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116908SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126908SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136908SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146908SBrad.Beckmann@amd.com# this software without specific prior written permission. 156908SBrad.Beckmann@amd.com# 166908SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176908SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186908SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196908SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206908SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216908SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226908SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236908SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246908SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256908SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266908SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276908SBrad.Beckmann@amd.com# 286908SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296908SBrad.Beckmann@amd.com 306908SBrad.Beckmann@amd.comimport math 316908SBrad.Beckmann@amd.comimport m5 326908SBrad.Beckmann@amd.comfrom m5.objects import * 336908SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366908SBrad.Beckmann@amd.com 376908SBrad.Beckmann@amd.com# 3811019Sjthestness@gmail.com# Declare caches used by the protocol 396908SBrad.Beckmann@amd.com# 4011019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4111019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 426908SBrad.Beckmann@amd.com 437538SBrad.Beckmann@amd.comdef define_options(parser): 447539SBrad.Beckmann@amd.com parser.add_option("--l1-retries", type="int", default=1, 457539SBrad.Beckmann@amd.com help="Token_CMP: # of l1 retries before going persistent") 467539SBrad.Beckmann@amd.com parser.add_option("--timeout-latency", type="int", default=300, 477539SBrad.Beckmann@amd.com help="Token_CMP: cycles until issuing again"); 487539SBrad.Beckmann@amd.com parser.add_option("--disable-dyn-timeouts", action="store_true", 497539SBrad.Beckmann@amd.com help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 507561SBrad.Beckmann@amd.com parser.add_option("--allow-atomic-migration", action="store_true", 517561SBrad.Beckmann@amd.com help="allow migratory sharing for atomic only accessed blocks") 5210917Sbrandon.potter@amd.com 5310519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 5410917Sbrandon.potter@amd.com 556908SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 566908SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_token protocol to be built.") 576908SBrad.Beckmann@amd.com 586908SBrad.Beckmann@amd.com # 596908SBrad.Beckmann@amd.com # number of tokens that the owner passes to requests so that shared blocks can 606908SBrad.Beckmann@amd.com # respond to read requests 616908SBrad.Beckmann@amd.com # 626908SBrad.Beckmann@amd.com n_tokens = options.num_cpus + 1 636908SBrad.Beckmann@amd.com 646908SBrad.Beckmann@amd.com cpu_sequencers = [] 6510917Sbrandon.potter@amd.com 666908SBrad.Beckmann@amd.com # 676908SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 686908SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 696908SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 706908SBrad.Beckmann@amd.com # 716908SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 726908SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 736908SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 746908SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 756908SBrad.Beckmann@amd.com 766908SBrad.Beckmann@amd.com # 776908SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 786908SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 796908SBrad.Beckmann@amd.com # 807564SBrad.Beckmann@amd.com l2_bits = int(math.log(options.num_l2caches, 2)) 818180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 8210917Sbrandon.potter@amd.com 836908SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 846908SBrad.Beckmann@amd.com # 856908SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 866908SBrad.Beckmann@amd.com # 876908SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 888180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 898180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 906908SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 918180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 928180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 936908SBrad.Beckmann@amd.com 946908SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 959695Snilay@cs.wisc.edu L1Icache = l1i_cache, 969695Snilay@cs.wisc.edu L1Dcache = l1d_cache, 977564SBrad.Beckmann@amd.com l2_select_num_bits = l2_bits, 987539SBrad.Beckmann@amd.com N_tokens = n_tokens, 997541SBrad.Beckmann@amd.com retry_threshold = \ 1007541SBrad.Beckmann@amd.com options.l1_retries, 1017539SBrad.Beckmann@amd.com fixed_timeout_latency = \ 1027539SBrad.Beckmann@amd.com options.timeout_latency, 1037539SBrad.Beckmann@amd.com dynamic_timeout_enabled = \ 1047561SBrad.Beckmann@amd.com not options.disable_dyn_timeouts, 1057561SBrad.Beckmann@amd.com no_mig_atomic = not \ 1068436SBrad.Beckmann@amd.com options.allow_atomic_migration, 10710529Smorr@cs.wisc.edu send_evictions = send_evicts(options), 1089841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 10910300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1108436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1117539SBrad.Beckmann@amd.com 1128322Ssteve.reinhardt@amd.com cpu_seq = RubySequencer(version = i, 1138322Ssteve.reinhardt@amd.com icache = l1i_cache, 1148322Ssteve.reinhardt@amd.com dcache = l1d_cache, 11510300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1168436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1178322Ssteve.reinhardt@amd.com 1188322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 11910116Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1208322Ssteve.reinhardt@amd.com 1216908SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1226908SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1236908SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1246908SBrad.Beckmann@amd.com 12510311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 12610311Snilay@cs.wisc.edu l1_cntrl.requestFromL1Cache = ruby_system.network.slave 12710311Snilay@cs.wisc.edu l1_cntrl.responseFromL1Cache = ruby_system.network.slave 12810311Snilay@cs.wisc.edu l1_cntrl.persistentFromL1Cache = ruby_system.network.slave 12910311Snilay@cs.wisc.edu 13010311Snilay@cs.wisc.edu l1_cntrl.requestToL1Cache = ruby_system.network.master 13110311Snilay@cs.wisc.edu l1_cntrl.responseToL1Cache = ruby_system.network.master 13210311Snilay@cs.wisc.edu l1_cntrl.persistentToL1Cache = ruby_system.network.master 13310311Snilay@cs.wisc.edu 13410311Snilay@cs.wisc.edu 1358180SBrad.Beckmann@amd.com l2_index_start = block_size_bits + l2_bits 1368180SBrad.Beckmann@amd.com 1376908SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1386908SBrad.Beckmann@amd.com # 1396908SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1406908SBrad.Beckmann@amd.com # 1416908SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1427564SBrad.Beckmann@amd.com assoc = options.l2_assoc, 1438180SBrad.Beckmann@amd.com start_index_bit = l2_index_start) 1446908SBrad.Beckmann@amd.com 1456908SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1469695Snilay@cs.wisc.edu L2cache = l2_cache, 1478436SBrad.Beckmann@amd.com N_tokens = n_tokens, 1489841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1498436SBrad.Beckmann@amd.com ruby_system = ruby_system) 15010917Sbrandon.potter@amd.com 1519468Smalek.musleh@gmail.com exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1526908SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1538257SBrad.Beckmann@amd.com 15410311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 15510311Snilay@cs.wisc.edu l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave 15610311Snilay@cs.wisc.edu l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 15710311Snilay@cs.wisc.edu l2_cntrl.responseFromL2Cache = ruby_system.network.slave 15810311Snilay@cs.wisc.edu 15910311Snilay@cs.wisc.edu l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master 16010311Snilay@cs.wisc.edu l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 16110311Snilay@cs.wisc.edu l2_cntrl.responseToL2Cache = ruby_system.network.master 16210311Snilay@cs.wisc.edu l2_cntrl.persistentToL2Cache = ruby_system.network.master 16310311Snilay@cs.wisc.edu 16410311Snilay@cs.wisc.edu 1659826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1669798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1676908SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1686908SBrad.Beckmann@amd.com 1699793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1709793Sakash.bagdia@arm.com # the ruby system 1719793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1729793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1739793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1749793Sakash.bagdia@arm.com clk_divider=3) 1759793Sakash.bagdia@arm.com 1766908SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1776908SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1786908SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1796908SBrad.Beckmann@amd.com 1806908SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 18110524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 18210524Snilay@cs.wisc.edu version = i, size = dir_size), 1838436SBrad.Beckmann@amd.com l2_select_num_bits = l2_bits, 1849841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1858436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1866908SBrad.Beckmann@amd.com 1879468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1886908SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1896908SBrad.Beckmann@amd.com 19010311Snilay@cs.wisc.edu # Connect the directory controllers and the network 19110311Snilay@cs.wisc.edu dir_cntrl.requestToDir = ruby_system.network.master 19210311Snilay@cs.wisc.edu dir_cntrl.responseToDir = ruby_system.network.master 19310311Snilay@cs.wisc.edu dir_cntrl.persistentToDir = ruby_system.network.master 19410311Snilay@cs.wisc.edu dir_cntrl.dmaRequestToDir = ruby_system.network.master 19510311Snilay@cs.wisc.edu 19610311Snilay@cs.wisc.edu dir_cntrl.requestFromDir = ruby_system.network.slave 19710311Snilay@cs.wisc.edu dir_cntrl.responseFromDir = ruby_system.network.slave 19810311Snilay@cs.wisc.edu dir_cntrl.persistentFromDir = ruby_system.network.slave 19910311Snilay@cs.wisc.edu dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 20010311Snilay@cs.wisc.edu 20110311Snilay@cs.wisc.edu 2028929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 2036908SBrad.Beckmann@amd.com # 2046908SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 2056908SBrad.Beckmann@amd.com # 2066908SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 20710519Snilay@cs.wisc.edu ruby_system = ruby_system, 20810519Snilay@cs.wisc.edu slave = dma_port) 20910917Sbrandon.potter@amd.com 2106908SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 2118477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 2129841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 2138477Snilay@cs.wisc.edu ruby_system = ruby_system) 2146908SBrad.Beckmann@amd.com 2159468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 2166908SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 2178257SBrad.Beckmann@amd.com 21810519Snilay@cs.wisc.edu # Connect the dma controller to the network 21910519Snilay@cs.wisc.edu dma_cntrl.responseFromDir = ruby_system.network.master 22010519Snilay@cs.wisc.edu dma_cntrl.reqToDirectory = ruby_system.network.slave 22110519Snilay@cs.wisc.edu 2226908SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 2236908SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 2246908SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 2256908SBrad.Beckmann@amd.com dma_cntrl_nodes 2266908SBrad.Beckmann@amd.com 22710519Snilay@cs.wisc.edu # Create the io controller and the sequencer 22810519Snilay@cs.wisc.edu if full_system: 22910519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 23010519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 23110519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 23210519Snilay@cs.wisc.edu dma_sequencer = io_seq, 23310519Snilay@cs.wisc.edu ruby_system = ruby_system) 23410519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 23510519Snilay@cs.wisc.edu 23610519Snilay@cs.wisc.edu # Connect the dma controller to the network 23710519Snilay@cs.wisc.edu io_controller.responseFromDir = ruby_system.network.master 23810519Snilay@cs.wisc.edu io_controller.reqToDirectory = ruby_system.network.slave 23910519Snilay@cs.wisc.edu 24010519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 24110519Snilay@cs.wisc.edu 24210519Snilay@cs.wisc.edu 2439100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 2449100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 245