MOESI_CMP_directory.py revision 7032:9f938aea1942
17927SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 27927SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 37927SN/A# All rights reserved. 49988Snilay@cs.wisc.edu# 58835SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 69988Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 77927SN/A# met: redistributions of source code must retain the above copyright 87927SN/A# notice, this list of conditions and the following disclaimer; 97927SN/A# redistributions in binary form must reproduce the above copyright 107927SN/A# notice, this list of conditions and the following disclaimer in the 117927SN/A# documentation and/or other materials provided with the distribution; 127927SN/A# neither the name of the copyright holders nor the names of its 1310315Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 147927SN/A# this software without specific prior written permission. 157927SN/A# 169885Sstever@gmail.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179885Sstever@gmail.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187927SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199988Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207927SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217927SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227927SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310315Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410315Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257927SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610315Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277927SN/A# 289474Snilay@cs.wisc.edu# Authors: Brad Beckmann 298673SN/A 308673SN/Aimport math 3110315Snilay@cs.wisc.eduimport m5 327927SN/Afrom m5.objects import * 337927SN/Afrom m5.defines import buildEnv 347927SN/Afrom m5.util import addToPath 357927SN/A 367927SN/A# 377927SN/A# Note: the L1 Cache latency is only used by the sequencer on fast path hits 387927SN/A# 397927SN/Aclass L1Cache(RubyCache): 407927SN/A latency = 3 418983Snate@binkert.org 427927SN/A# 437927SN/A# Note: the L2 Cache latency is not currently used 447927SN/A# 457927SN/Aclass L2Cache(RubyCache): 469988Snilay@cs.wisc.edu latency = 15 477927SN/A 487927SN/Adef create_system(options, phys_mem, piobus, dma_devices): 497927SN/A 507927SN/A if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 517927SN/A panic("This script requires the MOESI_CMP_directory protocol to be built.") 527927SN/A 537927SN/A cpu_sequencers = [] 547927SN/A 557927SN/A # 567927SN/A # The ruby network creation expects the list of nodes in the system to be 579988Snilay@cs.wisc.edu # consistent with the NetDest list. Therefore the l1 controller nodes must be 587927SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 597927SN/A # 607927SN/A l1_cntrl_nodes = [] 617927SN/A l2_cntrl_nodes = [] 628835SAli.Saidi@ARM.com dir_cntrl_nodes = [] 638835SAli.Saidi@ARM.com dma_cntrl_nodes = [] 649885Sstever@gmail.com 658835SAli.Saidi@ARM.com # 669988Snilay@cs.wisc.edu # Must create the individual controllers before the network to ensure the 678835SAli.Saidi@ARM.com # controller constructors are called before the network constructor 688835SAli.Saidi@ARM.com # 698835SAli.Saidi@ARM.com 708983Snate@binkert.org for i in xrange(options.num_cpus): 718983Snate@binkert.org # 728835SAli.Saidi@ARM.com # First create the Ruby objects associated with this cpu 737927SN/A # 747927SN/A l1i_cache = L1Cache(size = options.l1i_size, 759885Sstever@gmail.com assoc = options.l1i_assoc) 767927SN/A l1d_cache = L1Cache(size = options.l1d_size, 779988Snilay@cs.wisc.edu assoc = options.l1d_assoc) 7810451Snilay@cs.wisc.edu 798721SN/A cpu_seq = RubySequencer(version = i, 808721SN/A icache = l1i_cache, 818983Snate@binkert.org dcache = l1d_cache, 829885Sstever@gmail.com physMemPort = phys_mem.port, 839885Sstever@gmail.com physmem = phys_mem) 849885Sstever@gmail.com 859885Sstever@gmail.com if piobus != None: 869885Sstever@gmail.com cpu_seq.pio_port = piobus.port 8710315Snilay@cs.wisc.edu 889988Snilay@cs.wisc.edu l1_cntrl = L1Cache_Controller(version = i, 8910315Snilay@cs.wisc.edu sequencer = cpu_seq, 909885Sstever@gmail.com L1IcacheMemory = l1i_cache, 917927SN/A L1DcacheMemory = l1d_cache, 927927SN/A l2_select_num_bits = \ 937927SN/A math.log(options.num_l2caches, 2)) 949885Sstever@gmail.com # 9510315Snilay@cs.wisc.edu # Add controllers and sequencers to the appropriate lists 967927SN/A # 979885Sstever@gmail.com cpu_sequencers.append(cpu_seq) 987927SN/A l1_cntrl_nodes.append(l1_cntrl) 997927SN/A 1007927SN/A for i in xrange(options.num_l2caches): 1017927SN/A # 1027927SN/A # First create the Ruby objects associated with this cpu 1039988Snilay@cs.wisc.edu # 1048983Snate@binkert.org l2_cache = L2Cache(size = options.l2_size, 1057927SN/A assoc = options.l2_assoc) 1067927SN/A 1077927SN/A l2_cntrl = L2Cache_Controller(version = i, 1089474Snilay@cs.wisc.edu L2cacheMemory = l2_cache) 1097927SN/A 1107927SN/A l2_cntrl_nodes.append(l2_cntrl) 1117927SN/A 1127927SN/A phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 1137927SN/A mem_module_size = phys_mem_size / options.num_dirs 1147927SN/A 1157927SN/A for i in xrange(options.num_dirs): 1167927SN/A # 1179885Sstever@gmail.com # Create the Ruby objects associated with the directory controller 1187927SN/A # 1197927SN/A 12010315Snilay@cs.wisc.edu mem_cntrl = RubyMemoryControl(version = i) 1219474Snilay@cs.wisc.edu 1227927SN/A dir_size = MemorySize('0B') 1237927SN/A dir_size.value = mem_module_size 1247927SN/A 1258835SAli.Saidi@ARM.com dir_cntrl = Directory_Controller(version = i, 1267927SN/A directory = \ 1277927SN/A RubyDirectoryMemory(version = i, 1287927SN/A size = dir_size), 1299885Sstever@gmail.com memBuffer = mem_cntrl) 1309885Sstever@gmail.com 1319885Sstever@gmail.com dir_cntrl_nodes.append(dir_cntrl) 1329885Sstever@gmail.com 1339988Snilay@cs.wisc.edu for i, dma_device in enumerate(dma_devices): 1349885Sstever@gmail.com # 1357927SN/A # Create the Ruby objects associated with the dma controller 1367927SN/A # 1379885Sstever@gmail.com dma_seq = DMASequencer(version = i, 1388983Snate@binkert.org physMemPort = phys_mem.port, 1397927SN/A physmem = phys_mem) 1409885Sstever@gmail.com 1419988Snilay@cs.wisc.edu dma_cntrl = DMA_Controller(version = i, 1427927SN/A dma_sequencer = dma_seq) 1439361Snilay@cs.wisc.edu 1448241SN/A dma_cntrl.dma_sequencer.port = dma_device.dma 1457927SN/A dma_cntrl_nodes.append(dma_cntrl) 1467927SN/A 1477927SN/A all_cntrls = l1_cntrl_nodes + \ 1488835SAli.Saidi@ARM.com l2_cntrl_nodes + \ 1499361Snilay@cs.wisc.edu dir_cntrl_nodes + \ 15010036SAli.Saidi@ARM.com dma_cntrl_nodes 1517927SN/A 1528835SAli.Saidi@ARM.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 1539885Sstever@gmail.com