MOESI_CMP_directory.py revision 13971:0201983aad69 
1# Copyright (c) 2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# Copyright (c) 2009 Advanced Micro Devices, Inc.
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Brad Beckmann
41
42import math
43import m5
44from m5.objects import *
45from m5.defines import buildEnv
46from Ruby import create_topology, create_directories
47from Ruby import send_evicts
48
49#
50# Declare caches used by the protocol
51#
52class L1Cache(RubyCache): pass
53class L2Cache(RubyCache): pass
54
55def define_options(parser):
56    return
57
58def create_system(options, full_system, system, dma_ports, bootmem,
59                  ruby_system):
60
61    if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
62        panic("This script requires the MOESI_CMP_directory protocol to be built.")
63
64    cpu_sequencers = []
65
66    #
67    # The ruby network creation expects the list of nodes in the system to be
68    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
69    # listed before the directory nodes and directory nodes before dma nodes, etc.
70    #
71    l1_cntrl_nodes = []
72    l2_cntrl_nodes = []
73    dma_cntrl_nodes = []
74
75    #
76    # Must create the individual controllers before the network to ensure the
77    # controller constructors are called before the network constructor
78    #
79    block_size_bits = int(math.log(options.cacheline_size, 2))
80
81    for i in range(options.num_cpus):
82        #
83        # First create the Ruby objects associated with this cpu
84        #
85        l1i_cache = L1Cache(size = options.l1i_size,
86                            assoc = options.l1i_assoc,
87                            start_index_bit = block_size_bits,
88                            is_icache = True)
89        l1d_cache = L1Cache(size = options.l1d_size,
90                            assoc = options.l1d_assoc,
91                            start_index_bit = block_size_bits,
92                            is_icache = False)
93
94        # the ruby random tester reuses num_cpus to specify the
95        # number of cpu ports connected to the tester object, which
96        # is stored in system.cpu. because there is only ever one
97        # tester object, num_cpus is not necessarily equal to the
98        # size of system.cpu; therefore if len(system.cpu) == 1
99        # we use system.cpu[0] to set the clk_domain, thereby ensuring
100        # we don't index off the end of the cpu list.
101        if len(system.cpu) == 1:
102            clk_domain = system.cpu[0].clk_domain
103        else:
104            clk_domain = system.cpu[i].clk_domain
105
106        l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
107                                      L1Dcache=l1d_cache,
108                                      send_evictions=send_evicts(options),
109                                      transitions_per_cycle=options.ports,
110                                      clk_domain=clk_domain,
111                                      ruby_system=ruby_system)
112
113        cpu_seq = RubySequencer(version=i, icache=l1i_cache,
114                                dcache=l1d_cache, clk_domain=clk_domain,
115                                ruby_system=ruby_system)
116
117        l1_cntrl.sequencer = cpu_seq
118        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
119
120        # Add controllers and sequencers to the appropriate lists
121        cpu_sequencers.append(cpu_seq)
122        l1_cntrl_nodes.append(l1_cntrl)
123
124        # Connect the L1 controllers and the network
125        l1_cntrl.mandatoryQueue = MessageBuffer()
126        l1_cntrl.requestFromL1Cache = MessageBuffer()
127        l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
128        l1_cntrl.responseFromL1Cache = MessageBuffer()
129        l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
130        l1_cntrl.requestToL1Cache = MessageBuffer()
131        l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
132        l1_cntrl.responseToL1Cache = MessageBuffer()
133        l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
134        l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
135
136
137    # Create the L2s interleaved addr ranges
138    l2_addr_ranges = []
139    l2_bits = int(math.log(options.num_l2caches, 2))
140    numa_bit = block_size_bits + l2_bits - 1
141    sysranges = [] + system.mem_ranges
142    if bootmem: sysranges.append(bootmem.range)
143    for i in range(options.num_l2caches):
144        ranges = []
145        for r in sysranges:
146            addr_range = AddrRange(r.start, size = r.size(),
147                                    intlvHighBit = numa_bit,
148                                    intlvBits = l2_bits,
149                                    intlvMatch = i)
150            ranges.append(addr_range)
151        l2_addr_ranges.append(ranges)
152
153    for i in range(options.num_l2caches):
154        #
155        # First create the Ruby objects associated with this cpu
156        #
157        l2_cache = L2Cache(size = options.l2_size,
158                           assoc = options.l2_assoc,
159                           start_index_bit = block_size_bits + l2_bits)
160
161        l2_cntrl = L2Cache_Controller(version = i,
162                                      L2cache = l2_cache,
163                                      transitions_per_cycle = options.ports,
164                                      ruby_system = ruby_system,
165                                      addr_ranges = l2_addr_ranges[i])
166
167        exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
168        l2_cntrl_nodes.append(l2_cntrl)
169
170        # Connect the L2 controllers and the network
171        l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
172        l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
173        l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
174        l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
175        l2_cntrl.responseFromL2Cache = MessageBuffer()
176        l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
177
178        l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
179        l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
180        l2_cntrl.L1RequestToL2Cache = MessageBuffer()
181        l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
182        l2_cntrl.responseToL2Cache = MessageBuffer()
183        l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
184        l2_cntrl.triggerQueue = MessageBuffer(ordered = True)
185
186    # Run each of the ruby memory controllers at a ratio of the frequency of
187    # the ruby system.
188    # clk_divider value is a fix to pass regression.
189    ruby_system.memctrl_clk_domain = DerivedClockDomain(
190                                          clk_domain=ruby_system.clk_domain,
191                                          clk_divider=3)
192
193
194    mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
195        options, bootmem, ruby_system, system)
196    dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
197    if rom_dir_cntrl_node is not None:
198        dir_cntrl_nodes.append(rom_dir_cntrl_node)
199    for dir_cntrl in dir_cntrl_nodes:
200        # Connect the directory controllers and the network
201        dir_cntrl.requestToDir = MessageBuffer()
202        dir_cntrl.requestToDir.slave = ruby_system.network.master
203        dir_cntrl.responseToDir = MessageBuffer()
204        dir_cntrl.responseToDir.slave = ruby_system.network.master
205        dir_cntrl.responseFromDir = MessageBuffer()
206        dir_cntrl.responseFromDir.master = ruby_system.network.slave
207        dir_cntrl.forwardFromDir = MessageBuffer()
208        dir_cntrl.forwardFromDir.master = ruby_system.network.slave
209        dir_cntrl.responseFromMemory = MessageBuffer()
210
211
212    for i, dma_port in enumerate(dma_ports):
213        #
214        # Create the Ruby objects associated with the dma controller
215        #
216        dma_seq = DMASequencer(version = i,
217                               ruby_system = ruby_system,
218                               slave = dma_port)
219
220        dma_cntrl = DMA_Controller(version = i,
221                                   dma_sequencer = dma_seq,
222                                   transitions_per_cycle = options.ports,
223                                   ruby_system = ruby_system)
224
225        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
226        dma_cntrl_nodes.append(dma_cntrl)
227
228        # Connect the dma controller to the network
229        dma_cntrl.mandatoryQueue = MessageBuffer()
230        dma_cntrl.responseFromDir = MessageBuffer()
231        dma_cntrl.responseFromDir.slave = ruby_system.network.master
232        dma_cntrl.reqToDir = MessageBuffer()
233        dma_cntrl.reqToDir.master = ruby_system.network.slave
234        dma_cntrl.respToDir = MessageBuffer()
235        dma_cntrl.respToDir.master = ruby_system.network.slave
236        dma_cntrl.triggerQueue = MessageBuffer(ordered = True)
237
238
239    all_cntrls = l1_cntrl_nodes + \
240                 l2_cntrl_nodes + \
241                 dir_cntrl_nodes + \
242                 dma_cntrl_nodes
243
244    # Create the io controller and the sequencer
245    if full_system:
246        io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
247        ruby_system._io_port = io_seq
248        io_controller = DMA_Controller(version = len(dma_ports),
249                                       dma_sequencer = io_seq,
250                                       ruby_system = ruby_system)
251        ruby_system.io_controller = io_controller
252
253        # Connect the dma controller to the network
254        io_controller.mandatoryQueue = MessageBuffer()
255        io_controller.responseFromDir = MessageBuffer()
256        io_controller.responseFromDir.slave = ruby_system.network.master
257        io_controller.reqToDir = MessageBuffer()
258        io_controller.reqToDir.master = ruby_system.network.slave
259        io_controller.respToDir = MessageBuffer()
260        io_controller.respToDir.master = ruby_system.network.slave
261        io_controller.triggerQueue = MessageBuffer(ordered = True)
262
263        all_cntrls = all_cntrls + [io_controller]
264
265    ruby_system.network.number_of_virtual_networks = 3
266    topology = create_topology(all_cntrls, options)
267    return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
268