MOESI_CMP_directory.py revision 12065:e3e51756dfef 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
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9# redistributions in binary form must reproduce the above copyright
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14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology, create_directories
35from Ruby import send_evicts
36
37#
38# Declare caches used by the protocol
39#
40class L1Cache(RubyCache): pass
41class L2Cache(RubyCache): pass
42
43def define_options(parser):
44    return
45
46def create_system(options, full_system, system, dma_ports, ruby_system):
47
48    if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
49        panic("This script requires the MOESI_CMP_directory protocol to be built.")
50
51    cpu_sequencers = []
52
53    #
54    # The ruby network creation expects the list of nodes in the system to be
55    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
56    # listed before the directory nodes and directory nodes before dma nodes, etc.
57    #
58    l1_cntrl_nodes = []
59    l2_cntrl_nodes = []
60    dma_cntrl_nodes = []
61
62    #
63    # Must create the individual controllers before the network to ensure the
64    # controller constructors are called before the network constructor
65    #
66    l2_bits = int(math.log(options.num_l2caches, 2))
67    block_size_bits = int(math.log(options.cacheline_size, 2))
68
69    for i in xrange(options.num_cpus):
70        #
71        # First create the Ruby objects associated with this cpu
72        #
73        l1i_cache = L1Cache(size = options.l1i_size,
74                            assoc = options.l1i_assoc,
75                            start_index_bit = block_size_bits,
76                            is_icache = True)
77        l1d_cache = L1Cache(size = options.l1d_size,
78                            assoc = options.l1d_assoc,
79                            start_index_bit = block_size_bits,
80                            is_icache = False)
81
82        # the ruby random tester reuses num_cpus to specify the
83        # number of cpu ports connected to the tester object, which
84        # is stored in system.cpu. because there is only ever one
85        # tester object, num_cpus is not necessarily equal to the
86        # size of system.cpu; therefore if len(system.cpu) == 1
87        # we use system.cpu[0] to set the clk_domain, thereby ensuring
88        # we don't index off the end of the cpu list.
89        if len(system.cpu) == 1:
90            clk_domain = system.cpu[0].clk_domain
91        else:
92            clk_domain = system.cpu[i].clk_domain
93
94        l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
95                                      L1Dcache=l1d_cache,
96                                      l2_select_num_bits=l2_bits,
97                                      send_evictions=send_evicts(options),
98                                      transitions_per_cycle=options.ports,
99                                      clk_domain=clk_domain,
100                                      ruby_system=ruby_system)
101
102        cpu_seq = RubySequencer(version=i, icache=l1i_cache,
103                                dcache=l1d_cache, clk_domain=clk_domain,
104                                ruby_system=ruby_system)
105
106        l1_cntrl.sequencer = cpu_seq
107        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
108
109        # Add controllers and sequencers to the appropriate lists
110        cpu_sequencers.append(cpu_seq)
111        l1_cntrl_nodes.append(l1_cntrl)
112
113        # Connect the L1 controllers and the network
114        l1_cntrl.mandatoryQueue = MessageBuffer()
115        l1_cntrl.requestFromL1Cache = MessageBuffer()
116        l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
117        l1_cntrl.responseFromL1Cache = MessageBuffer()
118        l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
119        l1_cntrl.requestToL1Cache = MessageBuffer()
120        l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
121        l1_cntrl.responseToL1Cache = MessageBuffer()
122        l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
123        l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
124
125
126    l2_index_start = block_size_bits + l2_bits
127
128    for i in xrange(options.num_l2caches):
129        #
130        # First create the Ruby objects associated with this cpu
131        #
132        l2_cache = L2Cache(size = options.l2_size,
133                           assoc = options.l2_assoc,
134                           start_index_bit = l2_index_start)
135
136        l2_cntrl = L2Cache_Controller(version = i,
137                                      L2cache = l2_cache,
138                                      transitions_per_cycle = options.ports,
139                                      ruby_system = ruby_system)
140
141        exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
142        l2_cntrl_nodes.append(l2_cntrl)
143
144        # Connect the L2 controllers and the network
145        l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
146        l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
147        l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
148        l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
149        l2_cntrl.responseFromL2Cache = MessageBuffer()
150        l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
151
152        l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
153        l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
154        l2_cntrl.L1RequestToL2Cache = MessageBuffer()
155        l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
156        l2_cntrl.responseToL2Cache = MessageBuffer()
157        l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
158        l2_cntrl.triggerQueue = MessageBuffer(ordered = True)
159
160    # Run each of the ruby memory controllers at a ratio of the frequency of
161    # the ruby system.
162    # clk_divider value is a fix to pass regression.
163    ruby_system.memctrl_clk_domain = DerivedClockDomain(
164                                          clk_domain=ruby_system.clk_domain,
165                                          clk_divider=3)
166
167
168    dir_cntrl_nodes = create_directories(options, system.mem_ranges,
169                                         ruby_system)
170    for dir_cntrl in dir_cntrl_nodes:
171        # Connect the directory controllers and the network
172        dir_cntrl.requestToDir = MessageBuffer()
173        dir_cntrl.requestToDir.slave = ruby_system.network.master
174        dir_cntrl.responseToDir = MessageBuffer()
175        dir_cntrl.responseToDir.slave = ruby_system.network.master
176        dir_cntrl.responseFromDir = MessageBuffer()
177        dir_cntrl.responseFromDir.master = ruby_system.network.slave
178        dir_cntrl.forwardFromDir = MessageBuffer()
179        dir_cntrl.forwardFromDir.master = ruby_system.network.slave
180        dir_cntrl.responseFromMemory = MessageBuffer()
181
182
183    for i, dma_port in enumerate(dma_ports):
184        #
185        # Create the Ruby objects associated with the dma controller
186        #
187        dma_seq = DMASequencer(version = i,
188                               ruby_system = ruby_system,
189                               slave = dma_port)
190
191        dma_cntrl = DMA_Controller(version = i,
192                                   dma_sequencer = dma_seq,
193                                   transitions_per_cycle = options.ports,
194                                   ruby_system = ruby_system)
195
196        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
197        dma_cntrl_nodes.append(dma_cntrl)
198
199        # Connect the dma controller to the network
200        dma_cntrl.mandatoryQueue = MessageBuffer()
201        dma_cntrl.responseFromDir = MessageBuffer()
202        dma_cntrl.responseFromDir.slave = ruby_system.network.master
203        dma_cntrl.reqToDir = MessageBuffer()
204        dma_cntrl.reqToDir.master = ruby_system.network.slave
205        dma_cntrl.respToDir = MessageBuffer()
206        dma_cntrl.respToDir.master = ruby_system.network.slave
207        dma_cntrl.triggerQueue = MessageBuffer(ordered = True)
208
209
210    all_cntrls = l1_cntrl_nodes + \
211                 l2_cntrl_nodes + \
212                 dir_cntrl_nodes + \
213                 dma_cntrl_nodes
214
215    # Create the io controller and the sequencer
216    if full_system:
217        io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
218        ruby_system._io_port = io_seq
219        io_controller = DMA_Controller(version = len(dma_ports),
220                                       dma_sequencer = io_seq,
221                                       ruby_system = ruby_system)
222        ruby_system.io_controller = io_controller
223
224        # Connect the dma controller to the network
225        io_controller.mandatoryQueue = MessageBuffer()
226        io_controller.responseFromDir = MessageBuffer()
227        io_controller.responseFromDir.slave = ruby_system.network.master
228        io_controller.reqToDir = MessageBuffer()
229        io_controller.reqToDir.master = ruby_system.network.slave
230        io_controller.respToDir = MessageBuffer()
231        io_controller.respToDir.master = ruby_system.network.slave
232        io_controller.triggerQueue = MessageBuffer(ordered = True)
233
234        all_cntrls = all_cntrls + [io_controller]
235
236
237    ruby_system.network.number_of_virtual_networks = 3
238    topology = create_topology(all_cntrls, options)
239    return (cpu_sequencers, dir_cntrl_nodes, topology)
240