MOESI_AMD_Base.py revision 13400:cf74d21e948f
111482Sandreas.sandberg@arm.com# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 211482Sandreas.sandberg@arm.com# All rights reserved. 311482Sandreas.sandberg@arm.com# 411482Sandreas.sandberg@arm.com# For use for simulation and test purposes only 511482Sandreas.sandberg@arm.com# 611482Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without 711482Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are met: 811482Sandreas.sandberg@arm.com# 911482Sandreas.sandberg@arm.com# 1. Redistributions of source code must retain the above copyright notice, 1011482Sandreas.sandberg@arm.com# this list of conditions and the following disclaimer. 1111482Sandreas.sandberg@arm.com# 1211482Sandreas.sandberg@arm.com# 2. Redistributions in binary form must reproduce the above copyright notice, 1311482Sandreas.sandberg@arm.com# this list of conditions and the following disclaimer in the documentation 1411482Sandreas.sandberg@arm.com# and/or other materials provided with the distribution. 1511482Sandreas.sandberg@arm.com# 1611482Sandreas.sandberg@arm.com# 3. Neither the name of the copyright holder nor the names of its 1711482Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from this 1811482Sandreas.sandberg@arm.com# software without specific prior written permission. 1911482Sandreas.sandberg@arm.com# 2011482Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2111482Sandreas.sandberg@arm.com# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2211482Sandreas.sandberg@arm.com# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2311482Sandreas.sandberg@arm.com# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2411482Sandreas.sandberg@arm.com# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2511482Sandreas.sandberg@arm.com# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2611482Sandreas.sandberg@arm.com# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2711482Sandreas.sandberg@arm.com# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2811482Sandreas.sandberg@arm.com# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2911482Sandreas.sandberg@arm.com# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3011482Sandreas.sandberg@arm.com# POSSIBILITY OF SUCH DAMAGE. 3111482Sandreas.sandberg@arm.com# 3211482Sandreas.sandberg@arm.com# Authors: Lisa Hsu 3311482Sandreas.sandberg@arm.com 3411482Sandreas.sandberg@arm.comimport math 3511482Sandreas.sandberg@arm.comimport m5 3611482Sandreas.sandberg@arm.comfrom m5.objects import * 3711482Sandreas.sandberg@arm.comfrom m5.defines import buildEnv 3811482Sandreas.sandberg@arm.comfrom m5.util import addToPath 3911482Sandreas.sandberg@arm.comfrom Ruby import create_topology 4011482Sandreas.sandberg@arm.comfrom Ruby import send_evicts 4111482Sandreas.sandberg@arm.com 4211482Sandreas.sandberg@arm.comaddToPath('../') 4311482Sandreas.sandberg@arm.com 4411482Sandreas.sandberg@arm.comfrom topologies.Cluster import Cluster 4511482Sandreas.sandberg@arm.comfrom topologies.Crossbar import Crossbar 4611482Sandreas.sandberg@arm.com 4711482Sandreas.sandberg@arm.comclass CntrlBase: 4811482Sandreas.sandberg@arm.com _seqs = 0 4911482Sandreas.sandberg@arm.com @classmethod 5011482Sandreas.sandberg@arm.com def seqCount(cls): 5111482Sandreas.sandberg@arm.com # Use SeqCount not class since we need global count 5211482Sandreas.sandberg@arm.com CntrlBase._seqs += 1 5311482Sandreas.sandberg@arm.com return CntrlBase._seqs - 1 5411482Sandreas.sandberg@arm.com 5511482Sandreas.sandberg@arm.com _cntrls = 0 5611482Sandreas.sandberg@arm.com @classmethod 5711482Sandreas.sandberg@arm.com def cntrlCount(cls): 5811482Sandreas.sandberg@arm.com # Use CntlCount not class since we need global count 5911482Sandreas.sandberg@arm.com CntrlBase._cntrls += 1 6011482Sandreas.sandberg@arm.com return CntrlBase._cntrls - 1 6111482Sandreas.sandberg@arm.com 6211482Sandreas.sandberg@arm.com _version = 0 6311482Sandreas.sandberg@arm.com @classmethod 6411482Sandreas.sandberg@arm.com def versionCount(cls): 6511482Sandreas.sandberg@arm.com cls._version += 1 # Use count for this particular type 6611482Sandreas.sandberg@arm.com return cls._version - 1 6711482Sandreas.sandberg@arm.com 6811482Sandreas.sandberg@arm.comclass L1DCache(RubyCache): 6911482Sandreas.sandberg@arm.com resourceStalls = False 7011482Sandreas.sandberg@arm.com def create(self, options): 7111482Sandreas.sandberg@arm.com self.size = MemorySize(options.l1d_size) 7211482Sandreas.sandberg@arm.com self.assoc = options.l1d_assoc 7311482Sandreas.sandberg@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 7411482Sandreas.sandberg@arm.com 7511482Sandreas.sandberg@arm.comclass L1ICache(RubyCache): 7611482Sandreas.sandberg@arm.com resourceStalls = False 7711482Sandreas.sandberg@arm.com def create(self, options): 7811482Sandreas.sandberg@arm.com self.size = MemorySize(options.l1i_size) 7911482Sandreas.sandberg@arm.com self.assoc = options.l1i_assoc 8011482Sandreas.sandberg@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 8111482Sandreas.sandberg@arm.com 8211482Sandreas.sandberg@arm.comclass L2Cache(RubyCache): 8311482Sandreas.sandberg@arm.com resourceStalls = False 8411482Sandreas.sandberg@arm.com def create(self, options): 8511482Sandreas.sandberg@arm.com self.size = MemorySize(options.l2_size) 8611482Sandreas.sandberg@arm.com self.assoc = options.l2_assoc 8711482Sandreas.sandberg@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 8811482Sandreas.sandberg@arm.com 8911482Sandreas.sandberg@arm.comclass CPCntrl(CorePair_Controller, CntrlBase): 9011482Sandreas.sandberg@arm.com 9111482Sandreas.sandberg@arm.com def create(self, options, ruby_system, system): 9211482Sandreas.sandberg@arm.com self.version = self.versionCount() 9311482Sandreas.sandberg@arm.com 9411482Sandreas.sandberg@arm.com self.L1Icache = L1ICache() 9511482Sandreas.sandberg@arm.com self.L1Icache.create(options) 9611482Sandreas.sandberg@arm.com self.L1D0cache = L1DCache() 9711482Sandreas.sandberg@arm.com self.L1D0cache.create(options) 9811482Sandreas.sandberg@arm.com self.L1D1cache = L1DCache() 9911482Sandreas.sandberg@arm.com self.L1D1cache.create(options) 10011482Sandreas.sandberg@arm.com self.L2cache = L2Cache() 10111482Sandreas.sandberg@arm.com self.L2cache.create(options) 10211482Sandreas.sandberg@arm.com 10311482Sandreas.sandberg@arm.com self.sequencer = RubySequencer() 10411482Sandreas.sandberg@arm.com self.sequencer.icache_hit_latency = 2 10511482Sandreas.sandberg@arm.com self.sequencer.dcache_hit_latency = 2 10611482Sandreas.sandberg@arm.com self.sequencer.version = self.seqCount() 10711482Sandreas.sandberg@arm.com self.sequencer.icache = self.L1Icache 10811482Sandreas.sandberg@arm.com self.sequencer.dcache = self.L1D0cache 10911482Sandreas.sandberg@arm.com self.sequencer.ruby_system = ruby_system 11011482Sandreas.sandberg@arm.com self.sequencer.coreid = 0 11111482Sandreas.sandberg@arm.com self.sequencer.is_cpu_sequencer = True 11211482Sandreas.sandberg@arm.com 11311482Sandreas.sandberg@arm.com self.sequencer1 = RubySequencer() 11411482Sandreas.sandberg@arm.com self.sequencer1.version = self.seqCount() 11511482Sandreas.sandberg@arm.com self.sequencer1.icache = self.L1Icache 11611482Sandreas.sandberg@arm.com self.sequencer1.dcache = self.L1D1cache 11711482Sandreas.sandberg@arm.com self.sequencer1.icache_hit_latency = 2 11811482Sandreas.sandberg@arm.com self.sequencer1.dcache_hit_latency = 2 11911482Sandreas.sandberg@arm.com self.sequencer1.ruby_system = ruby_system 12011482Sandreas.sandberg@arm.com self.sequencer1.coreid = 1 12111482Sandreas.sandberg@arm.com self.sequencer1.is_cpu_sequencer = True 12211482Sandreas.sandberg@arm.com 12311482Sandreas.sandberg@arm.com self.issue_latency = options.cpu_to_dir_latency 12411482Sandreas.sandberg@arm.com self.send_evictions = send_evicts(options) 12511482Sandreas.sandberg@arm.com 12611482Sandreas.sandberg@arm.com self.ruby_system = ruby_system 12711482Sandreas.sandberg@arm.com 12811482Sandreas.sandberg@arm.com if options.recycle_latency: 12911482Sandreas.sandberg@arm.com self.recycle_latency = options.recycle_latency 13011482Sandreas.sandberg@arm.com 13111482Sandreas.sandberg@arm.comclass L3Cache(RubyCache): 13211482Sandreas.sandberg@arm.com assoc = 8 13311482Sandreas.sandberg@arm.com dataArrayBanks = 256 13411482Sandreas.sandberg@arm.com tagArrayBanks = 256 13511482Sandreas.sandberg@arm.com 13611482Sandreas.sandberg@arm.com def create(self, options, ruby_system, system): 13711482Sandreas.sandberg@arm.com self.size = MemorySize(options.l3_size) 13811482Sandreas.sandberg@arm.com self.size.value /= options.num_dirs 13911482Sandreas.sandberg@arm.com self.dataArrayBanks /= options.num_dirs 14011482Sandreas.sandberg@arm.com self.tagArrayBanks /= options.num_dirs 14111482Sandreas.sandberg@arm.com self.dataArrayBanks /= options.num_dirs 14211482Sandreas.sandberg@arm.com self.tagArrayBanks /= options.num_dirs 14311482Sandreas.sandberg@arm.com self.dataAccessLatency = options.l3_data_latency 14411482Sandreas.sandberg@arm.com self.tagAccessLatency = options.l3_tag_latency 14511482Sandreas.sandberg@arm.com self.resourceStalls = options.no_resource_stalls 14611482Sandreas.sandberg@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 14711482Sandreas.sandberg@arm.com 14811482Sandreas.sandberg@arm.comclass L3Cntrl(L3Cache_Controller, CntrlBase): 14911482Sandreas.sandberg@arm.com def create(self, options, ruby_system, system): 15011482Sandreas.sandberg@arm.com self.version = self.versionCount() 15111482Sandreas.sandberg@arm.com self.L3cache = L3Cache() 15211482Sandreas.sandberg@arm.com self.L3cache.create(options, ruby_system, system) 15311482Sandreas.sandberg@arm.com 15411482Sandreas.sandberg@arm.com self.l3_response_latency = max(self.L3cache.dataAccessLatency, 15511482Sandreas.sandberg@arm.com self.L3cache.tagAccessLatency) 15611482Sandreas.sandberg@arm.com self.ruby_system = ruby_system 15711482Sandreas.sandberg@arm.com 15811482Sandreas.sandberg@arm.com if options.recycle_latency: 15911482Sandreas.sandberg@arm.com self.recycle_latency = options.recycle_latency 16011482Sandreas.sandberg@arm.com 16111482Sandreas.sandberg@arm.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 16211482Sandreas.sandberg@arm.com req_to_l3, probe_to_l3, resp_to_l3): 16311482Sandreas.sandberg@arm.com self.reqToDir = req_to_dir 16411482Sandreas.sandberg@arm.com self.respToDir = resp_to_dir 16511482Sandreas.sandberg@arm.com self.l3UnblockToDir = l3_unblock_to_dir 16611482Sandreas.sandberg@arm.com self.reqToL3 = req_to_l3 16711482Sandreas.sandberg@arm.com self.probeToL3 = probe_to_l3 16811482Sandreas.sandberg@arm.com self.respToL3 = resp_to_l3 16911482Sandreas.sandberg@arm.com 17011482Sandreas.sandberg@arm.comclass DirCntrl(Directory_Controller, CntrlBase): 17111482Sandreas.sandberg@arm.com def create(self, options, dir_ranges, ruby_system, system): 17211482Sandreas.sandberg@arm.com self.version = self.versionCount() 17311482Sandreas.sandberg@arm.com 17411482Sandreas.sandberg@arm.com self.response_latency = 30 17511482Sandreas.sandberg@arm.com 17611482Sandreas.sandberg@arm.com self.addr_ranges = dir_ranges 17711482Sandreas.sandberg@arm.com self.directory = RubyDirectoryMemory() 17811482Sandreas.sandberg@arm.com 17911482Sandreas.sandberg@arm.com self.L3CacheMemory = L3Cache() 18011482Sandreas.sandberg@arm.com self.L3CacheMemory.create(options, ruby_system, system) 18111482Sandreas.sandberg@arm.com 18211482Sandreas.sandberg@arm.com self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 18311482Sandreas.sandberg@arm.com self.L3CacheMemory.tagAccessLatency) 18411482Sandreas.sandberg@arm.com 18511482Sandreas.sandberg@arm.com self.number_of_TBEs = options.num_tbes 18611482Sandreas.sandberg@arm.com 18711482Sandreas.sandberg@arm.com self.ruby_system = ruby_system 18811482Sandreas.sandberg@arm.com 18911482Sandreas.sandberg@arm.com if options.recycle_latency: 19011482Sandreas.sandberg@arm.com self.recycle_latency = options.recycle_latency 19111482Sandreas.sandberg@arm.com 19211482Sandreas.sandberg@arm.com self.CPUonly = True 19311482Sandreas.sandberg@arm.com 19411482Sandreas.sandberg@arm.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 19511482Sandreas.sandberg@arm.com req_to_l3, probe_to_l3, resp_to_l3): 19611482Sandreas.sandberg@arm.com self.reqToDir = req_to_dir 19711482Sandreas.sandberg@arm.com self.respToDir = resp_to_dir 19811482Sandreas.sandberg@arm.com self.l3UnblockToDir = l3_unblock_to_dir 19911482Sandreas.sandberg@arm.com self.reqToL3 = req_to_l3 20011482Sandreas.sandberg@arm.com self.probeToL3 = probe_to_l3 20111482Sandreas.sandberg@arm.com self.respToL3 = resp_to_l3 20211482Sandreas.sandberg@arm.com 20311482Sandreas.sandberg@arm.comdef define_options(parser): 20411482Sandreas.sandberg@arm.com parser.add_option("--num-subcaches", type="int", default=4) 20511482Sandreas.sandberg@arm.com parser.add_option("--l3-data-latency", type="int", default=20) 20611482Sandreas.sandberg@arm.com parser.add_option("--l3-tag-latency", type="int", default=15) 20711482Sandreas.sandberg@arm.com parser.add_option("--cpu-to-dir-latency", type="int", default=15) 20811482Sandreas.sandberg@arm.com parser.add_option("--no-resource-stalls", action="store_false", 20911482Sandreas.sandberg@arm.com default=True) 21011482Sandreas.sandberg@arm.com parser.add_option("--num-tbes", type="int", default=256) 21111482Sandreas.sandberg@arm.com parser.add_option("--l2-latency", type="int", default=50) # load to use 21211482Sandreas.sandberg@arm.com 21311482Sandreas.sandberg@arm.comdef create_system(options, full_system, system, dma_devices, bootmem, 21411482Sandreas.sandberg@arm.com ruby_system): 21511482Sandreas.sandberg@arm.com if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base': 21611482Sandreas.sandberg@arm.com panic("This script requires the MOESI_AMD_Base protocol.") 21711482Sandreas.sandberg@arm.com 21811482Sandreas.sandberg@arm.com cpu_sequencers = [] 21911482Sandreas.sandberg@arm.com 22011482Sandreas.sandberg@arm.com # 22111482Sandreas.sandberg@arm.com # The ruby network creation expects the list of nodes in the system to 22211482Sandreas.sandberg@arm.com # be consistent with the NetDest list. Therefore the l1 controller 22311482Sandreas.sandberg@arm.com # nodes must be listed before the directory nodes and directory nodes 22411482Sandreas.sandberg@arm.com # before dma nodes, etc. 22511482Sandreas.sandberg@arm.com # 22611482Sandreas.sandberg@arm.com l1_cntrl_nodes = [] 22711482Sandreas.sandberg@arm.com l3_cntrl_nodes = [] 22811482Sandreas.sandberg@arm.com dir_cntrl_nodes = [] 22911482Sandreas.sandberg@arm.com 23011482Sandreas.sandberg@arm.com control_count = 0 23111482Sandreas.sandberg@arm.com 23211482Sandreas.sandberg@arm.com # 23311482Sandreas.sandberg@arm.com # Must create the individual controllers before the network to ensure 23411482Sandreas.sandberg@arm.com # the controller constructors are called before the network constructor 23511482Sandreas.sandberg@arm.com # 23611482Sandreas.sandberg@arm.com 23711482Sandreas.sandberg@arm.com # This is the base crossbar that connects the L3s, Dirs, and cpu 23811482Sandreas.sandberg@arm.com # Cluster 23911482Sandreas.sandberg@arm.com mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 24011482Sandreas.sandberg@arm.com 24111482Sandreas.sandberg@arm.com if options.numa_high_bit: 24211482Sandreas.sandberg@arm.com numa_bit = options.numa_high_bit 24311482Sandreas.sandberg@arm.com else: 24411482Sandreas.sandberg@arm.com # if the numa_bit is not specified, set the directory bits as the 24511482Sandreas.sandberg@arm.com # lowest bits above the block offset bits, and the numa_bit as the 24611482Sandreas.sandberg@arm.com # highest of those directory bits 24711482Sandreas.sandberg@arm.com dir_bits = int(math.log(options.num_dirs, 2)) 24811482Sandreas.sandberg@arm.com block_size_bits = int(math.log(options.cacheline_size, 2)) 24911482Sandreas.sandberg@arm.com numa_bit = block_size_bits + dir_bits - 1 25011482Sandreas.sandberg@arm.com 25111482Sandreas.sandberg@arm.com for i in xrange(options.num_dirs): 25211482Sandreas.sandberg@arm.com dir_ranges = [] 25311482Sandreas.sandberg@arm.com for r in system.mem_ranges: 25411482Sandreas.sandberg@arm.com addr_range = m5.objects.AddrRange(r.start, size = r.size(), 25511482Sandreas.sandberg@arm.com intlvHighBit = numa_bit, 25611482Sandreas.sandberg@arm.com intlvBits = dir_bits, 25711482Sandreas.sandberg@arm.com intlvMatch = i) 25811482Sandreas.sandberg@arm.com dir_ranges.append(addr_range) 25911482Sandreas.sandberg@arm.com 26011482Sandreas.sandberg@arm.com 26111482Sandreas.sandberg@arm.com dir_cntrl = DirCntrl(TCC_select_num_bits = 0) 26211482Sandreas.sandberg@arm.com dir_cntrl.create(options, dir_ranges, ruby_system, system) 26311482Sandreas.sandberg@arm.com 26411482Sandreas.sandberg@arm.com # Connect the Directory controller to the ruby network 26511482Sandreas.sandberg@arm.com dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 26611482Sandreas.sandberg@arm.com dir_cntrl.requestFromCores.slave = ruby_system.network.master 26711482Sandreas.sandberg@arm.com 26811482Sandreas.sandberg@arm.com dir_cntrl.responseFromCores = MessageBuffer() 26911482Sandreas.sandberg@arm.com dir_cntrl.responseFromCores.slave = ruby_system.network.master 27011482Sandreas.sandberg@arm.com 27111482Sandreas.sandberg@arm.com dir_cntrl.unblockFromCores = MessageBuffer() 27211482Sandreas.sandberg@arm.com dir_cntrl.unblockFromCores.slave = ruby_system.network.master 27311482Sandreas.sandberg@arm.com 27411482Sandreas.sandberg@arm.com dir_cntrl.probeToCore = MessageBuffer() 27511482Sandreas.sandberg@arm.com dir_cntrl.probeToCore.master = ruby_system.network.slave 27611482Sandreas.sandberg@arm.com 27711482Sandreas.sandberg@arm.com dir_cntrl.responseToCore = MessageBuffer() 27811482Sandreas.sandberg@arm.com dir_cntrl.responseToCore.master = ruby_system.network.slave 27911482Sandreas.sandberg@arm.com 28011482Sandreas.sandberg@arm.com dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 28111482Sandreas.sandberg@arm.com dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 28211482Sandreas.sandberg@arm.com dir_cntrl.responseFromMemory = MessageBuffer() 28311482Sandreas.sandberg@arm.com 28411482Sandreas.sandberg@arm.com exec("system.dir_cntrl%d = dir_cntrl" % i) 28511482Sandreas.sandberg@arm.com dir_cntrl_nodes.append(dir_cntrl) 28611482Sandreas.sandberg@arm.com 28711482Sandreas.sandberg@arm.com mainCluster.add(dir_cntrl) 288 289 # Technically this config can support an odd number of cpus, but the top 290 # level config files, such as the ruby_random_tester, will get confused if 291 # the number of cpus does not equal the number of sequencers. Thus make 292 # sure that an even number of cpus is specified. 293 assert((options.num_cpus % 2) == 0) 294 295 # For an odd number of CPUs, still create the right number of controllers 296 cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 297 for i in xrange((options.num_cpus + 1) / 2): 298 299 cp_cntrl = CPCntrl() 300 cp_cntrl.create(options, ruby_system, system) 301 302 exec("system.cp_cntrl%d = cp_cntrl" % i) 303 # 304 # Add controllers and sequencers to the appropriate lists 305 # 306 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 307 308 # Connect the CP controllers and the network 309 cp_cntrl.requestFromCore = MessageBuffer() 310 cp_cntrl.requestFromCore.master = ruby_system.network.slave 311 312 cp_cntrl.responseFromCore = MessageBuffer() 313 cp_cntrl.responseFromCore.master = ruby_system.network.slave 314 315 cp_cntrl.unblockFromCore = MessageBuffer() 316 cp_cntrl.unblockFromCore.master = ruby_system.network.slave 317 318 cp_cntrl.probeToCore = MessageBuffer() 319 cp_cntrl.probeToCore.slave = ruby_system.network.master 320 321 cp_cntrl.responseToCore = MessageBuffer() 322 cp_cntrl.responseToCore.slave = ruby_system.network.master 323 324 cp_cntrl.mandatoryQueue = MessageBuffer() 325 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 326 327 cpuCluster.add(cp_cntrl) 328 329 # Assuming no DMA devices 330 assert(len(dma_devices) == 0) 331 332 # Add cpu/gpu clusters to main cluster 333 mainCluster.add(cpuCluster) 334 335 ruby_system.network.number_of_virtual_networks = 10 336 337 return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 338