MOESI_AMD_Base.py revision 11308:7d8836fd043d
16691Stjones1@inf.ed.ac.uk# 26691Stjones1@inf.ed.ac.uk# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 36691Stjones1@inf.ed.ac.uk# All rights reserved. 46691Stjones1@inf.ed.ac.uk# 56691Stjones1@inf.ed.ac.uk# For use for simulation and test purposes only 66691Stjones1@inf.ed.ac.uk# 76691Stjones1@inf.ed.ac.uk# Redistribution and use in source and binary forms, with or without 86691Stjones1@inf.ed.ac.uk# modification, are permitted provided that the following conditions are met: 96691Stjones1@inf.ed.ac.uk# 106691Stjones1@inf.ed.ac.uk# 1. Redistributions of source code must retain the above copyright notice, 116691Stjones1@inf.ed.ac.uk# this list of conditions and the following disclaimer. 126691Stjones1@inf.ed.ac.uk# 136691Stjones1@inf.ed.ac.uk# 2. Redistributions in binary form must reproduce the above copyright notice, 146691Stjones1@inf.ed.ac.uk# this list of conditions and the following disclaimer in the documentation 156691Stjones1@inf.ed.ac.uk# and/or other materials provided with the distribution. 166691Stjones1@inf.ed.ac.uk# 176691Stjones1@inf.ed.ac.uk# 3. Neither the name of the copyright holder nor the names of its contributors 186691Stjones1@inf.ed.ac.uk# may be used to endorse or promote products derived from this software 196691Stjones1@inf.ed.ac.uk# without specific prior written permission. 206691Stjones1@inf.ed.ac.uk# 216691Stjones1@inf.ed.ac.uk# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 226691Stjones1@inf.ed.ac.uk# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 236691Stjones1@inf.ed.ac.uk# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 246691Stjones1@inf.ed.ac.uk# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 256691Stjones1@inf.ed.ac.uk# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 266691Stjones1@inf.ed.ac.uk# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 276691Stjones1@inf.ed.ac.uk# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 286691Stjones1@inf.ed.ac.uk# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 296691Stjones1@inf.ed.ac.uk# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 306691Stjones1@inf.ed.ac.uk# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 316691Stjones1@inf.ed.ac.uk# POSSIBILITY OF SUCH DAMAGE. 326691Stjones1@inf.ed.ac.uk# 336691Stjones1@inf.ed.ac.uk# Author: Lisa Hsu 346691Stjones1@inf.ed.ac.uk# 356691Stjones1@inf.ed.ac.uk 366691Stjones1@inf.ed.ac.ukimport math 376691Stjones1@inf.ed.ac.ukimport m5 386691Stjones1@inf.ed.ac.ukfrom m5.objects import * 396691Stjones1@inf.ed.ac.ukfrom m5.defines import buildEnv 406691Stjones1@inf.ed.ac.ukfrom Ruby import create_topology 416691Stjones1@inf.ed.ac.ukfrom Ruby import send_evicts 426691Stjones1@inf.ed.ac.uk 436691Stjones1@inf.ed.ac.ukfrom Cluster import Cluster 446691Stjones1@inf.ed.ac.ukfrom Crossbar import Crossbar 456691Stjones1@inf.ed.ac.uk 466691Stjones1@inf.ed.ac.ukclass CntrlBase: 476691Stjones1@inf.ed.ac.uk _seqs = 0 486691Stjones1@inf.ed.ac.uk @classmethod 496691Stjones1@inf.ed.ac.uk def seqCount(cls): 506691Stjones1@inf.ed.ac.uk # Use SeqCount not class since we need global count 516691Stjones1@inf.ed.ac.uk CntrlBase._seqs += 1 526691Stjones1@inf.ed.ac.uk return CntrlBase._seqs - 1 536691Stjones1@inf.ed.ac.uk 546691Stjones1@inf.ed.ac.uk _cntrls = 0 556691Stjones1@inf.ed.ac.uk @classmethod 566691Stjones1@inf.ed.ac.uk def cntrlCount(cls): 576691Stjones1@inf.ed.ac.uk # Use CntlCount not class since we need global count 586691Stjones1@inf.ed.ac.uk CntrlBase._cntrls += 1 596691Stjones1@inf.ed.ac.uk return CntrlBase._cntrls - 1 606691Stjones1@inf.ed.ac.uk 616691Stjones1@inf.ed.ac.uk _version = 0 626691Stjones1@inf.ed.ac.uk @classmethod 636691Stjones1@inf.ed.ac.uk def versionCount(cls): 646691Stjones1@inf.ed.ac.uk cls._version += 1 # Use count for this particular type 656691Stjones1@inf.ed.ac.uk return cls._version - 1 666691Stjones1@inf.ed.ac.uk 676691Stjones1@inf.ed.ac.ukclass L1DCache(RubyCache): 686691Stjones1@inf.ed.ac.uk resourceStalls = False 696691Stjones1@inf.ed.ac.uk def create(self, options): 706691Stjones1@inf.ed.ac.uk self.size = MemorySize(options.l1d_size) 716691Stjones1@inf.ed.ac.uk self.assoc = options.l1d_assoc 726691Stjones1@inf.ed.ac.uk self.replacement_policy = PseudoLRUReplacementPolicy() 736691Stjones1@inf.ed.ac.uk 746691Stjones1@inf.ed.ac.ukclass L1ICache(RubyCache): 756691Stjones1@inf.ed.ac.uk resourceStalls = False 766691Stjones1@inf.ed.ac.uk def create(self, options): 776691Stjones1@inf.ed.ac.uk self.size = MemorySize(options.l1i_size) 786691Stjones1@inf.ed.ac.uk self.assoc = options.l1i_assoc 796691Stjones1@inf.ed.ac.uk self.replacement_policy = PseudoLRUReplacementPolicy() 806691Stjones1@inf.ed.ac.uk 816691Stjones1@inf.ed.ac.ukclass L2Cache(RubyCache): 826691Stjones1@inf.ed.ac.uk resourceStalls = False 836691Stjones1@inf.ed.ac.uk def create(self, options): 846691Stjones1@inf.ed.ac.uk self.size = MemorySize(options.l2_size) 856691Stjones1@inf.ed.ac.uk self.assoc = options.l2_assoc 866691Stjones1@inf.ed.ac.uk self.replacement_policy = PseudoLRUReplacementPolicy() 876691Stjones1@inf.ed.ac.uk 886691Stjones1@inf.ed.ac.ukclass CPCntrl(CorePair_Controller, CntrlBase): 896691Stjones1@inf.ed.ac.uk 906691Stjones1@inf.ed.ac.uk def create(self, options, ruby_system, system): 916691Stjones1@inf.ed.ac.uk self.version = self.versionCount() 926691Stjones1@inf.ed.ac.uk 936691Stjones1@inf.ed.ac.uk self.L1Icache = L1ICache() 946691Stjones1@inf.ed.ac.uk self.L1Icache.create(options) 956691Stjones1@inf.ed.ac.uk self.L1D0cache = L1DCache() 966691Stjones1@inf.ed.ac.uk self.L1D0cache.create(options) 976691Stjones1@inf.ed.ac.uk self.L1D1cache = L1DCache() 986691Stjones1@inf.ed.ac.uk self.L1D1cache.create(options) 996691Stjones1@inf.ed.ac.uk self.L2cache = L2Cache() 1006691Stjones1@inf.ed.ac.uk self.L2cache.create(options) 1016691Stjones1@inf.ed.ac.uk 1026691Stjones1@inf.ed.ac.uk self.sequencer = RubySequencer() 1036691Stjones1@inf.ed.ac.uk self.sequencer.icache_hit_latency = 2 1046691Stjones1@inf.ed.ac.uk self.sequencer.dcache_hit_latency = 2 1056691Stjones1@inf.ed.ac.uk self.sequencer.version = self.seqCount() 1066691Stjones1@inf.ed.ac.uk self.sequencer.icache = self.L1Icache 1076691Stjones1@inf.ed.ac.uk self.sequencer.dcache = self.L1D0cache 1086691Stjones1@inf.ed.ac.uk self.sequencer.ruby_system = ruby_system 1096691Stjones1@inf.ed.ac.uk self.sequencer.coreid = 0 1106691Stjones1@inf.ed.ac.uk self.sequencer.is_cpu_sequencer = True 1116691Stjones1@inf.ed.ac.uk 1126691Stjones1@inf.ed.ac.uk self.sequencer1 = RubySequencer() 1136691Stjones1@inf.ed.ac.uk self.sequencer1.version = self.seqCount() 1146691Stjones1@inf.ed.ac.uk self.sequencer1.icache = self.L1Icache 1156691Stjones1@inf.ed.ac.uk self.sequencer1.dcache = self.L1D1cache 1166691Stjones1@inf.ed.ac.uk self.sequencer1.icache_hit_latency = 2 1176691Stjones1@inf.ed.ac.uk self.sequencer1.dcache_hit_latency = 2 1186691Stjones1@inf.ed.ac.uk self.sequencer1.ruby_system = ruby_system 1196691Stjones1@inf.ed.ac.uk self.sequencer1.coreid = 1 1206691Stjones1@inf.ed.ac.uk self.sequencer1.is_cpu_sequencer = True 1216691Stjones1@inf.ed.ac.uk 1226691Stjones1@inf.ed.ac.uk self.issue_latency = options.cpu_to_dir_latency 1236691Stjones1@inf.ed.ac.uk self.send_evictions = send_evicts(options) 1246691Stjones1@inf.ed.ac.uk 1256691Stjones1@inf.ed.ac.uk self.ruby_system = ruby_system 1266691Stjones1@inf.ed.ac.uk 1276691Stjones1@inf.ed.ac.uk if options.recycle_latency: 1286691Stjones1@inf.ed.ac.uk self.recycle_latency = options.recycle_latency 1296691Stjones1@inf.ed.ac.uk 1306691Stjones1@inf.ed.ac.ukclass L3Cache(RubyCache): 1316691Stjones1@inf.ed.ac.uk assoc = 8 1326691Stjones1@inf.ed.ac.uk dataArrayBanks = 256 1336691Stjones1@inf.ed.ac.uk tagArrayBanks = 256 1346691Stjones1@inf.ed.ac.uk 1356691Stjones1@inf.ed.ac.uk def create(self, options, ruby_system, system): 1366691Stjones1@inf.ed.ac.uk self.size = MemorySize(options.l3_size) 1376691Stjones1@inf.ed.ac.uk self.size.value /= options.num_dirs 1386691Stjones1@inf.ed.ac.uk self.dataArrayBanks /= options.num_dirs 1396691Stjones1@inf.ed.ac.uk self.tagArrayBanks /= options.num_dirs 1406691Stjones1@inf.ed.ac.uk self.dataArrayBanks /= options.num_dirs 1416691Stjones1@inf.ed.ac.uk self.tagArrayBanks /= options.num_dirs 1426691Stjones1@inf.ed.ac.uk self.dataAccessLatency = options.l3_data_latency 1436691Stjones1@inf.ed.ac.uk self.tagAccessLatency = options.l3_tag_latency 1446691Stjones1@inf.ed.ac.uk self.resourceStalls = options.no_resource_stalls 1456691Stjones1@inf.ed.ac.uk self.replacement_policy = PseudoLRUReplacementPolicy() 1466691Stjones1@inf.ed.ac.uk 1476691Stjones1@inf.ed.ac.ukclass L3Cntrl(L3Cache_Controller, CntrlBase): 1486691Stjones1@inf.ed.ac.uk def create(self, options, ruby_system, system): 1496691Stjones1@inf.ed.ac.uk self.version = self.versionCount() 1506691Stjones1@inf.ed.ac.uk self.L3cache = L3Cache() 1517811Ssteve.reinhardt@amd.com self.L3cache.create(options, ruby_system, system) 1526691Stjones1@inf.ed.ac.uk 1536691Stjones1@inf.ed.ac.uk self.l3_response_latency = max(self.L3cache.dataAccessLatency, 154 self.L3cache.tagAccessLatency) 155 self.ruby_system = ruby_system 156 157 if options.recycle_latency: 158 self.recycle_latency = options.recycle_latency 159 160 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 161 req_to_l3, probe_to_l3, resp_to_l3): 162 self.reqToDir = req_to_dir 163 self.respToDir = resp_to_dir 164 self.l3UnblockToDir = l3_unblock_to_dir 165 self.reqToL3 = req_to_l3 166 self.probeToL3 = probe_to_l3 167 self.respToL3 = resp_to_l3 168 169class DirMem(RubyDirectoryMemory, CntrlBase): 170 def create(self, options, ruby_system, system): 171 self.version = self.versionCount() 172 173 phys_mem_size = AddrRange(options.mem_size).size() 174 mem_module_size = phys_mem_size / options.num_dirs 175 dir_size = MemorySize('0B') 176 dir_size.value = mem_module_size 177 self.size = dir_size 178 179class DirCntrl(Directory_Controller, CntrlBase): 180 def create(self, options, ruby_system, system): 181 self.version = self.versionCount() 182 183 self.response_latency = 30 184 185 self.directory = DirMem() 186 self.directory.create(options, ruby_system, system) 187 188 self.L3CacheMemory = L3Cache() 189 self.L3CacheMemory.create(options, ruby_system, system) 190 191 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 192 self.L3CacheMemory.tagAccessLatency) 193 194 self.number_of_TBEs = options.num_tbes 195 196 self.ruby_system = ruby_system 197 198 if options.recycle_latency: 199 self.recycle_latency = options.recycle_latency 200 201 self.CPUonly = True 202 203 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 204 req_to_l3, probe_to_l3, resp_to_l3): 205 self.reqToDir = req_to_dir 206 self.respToDir = resp_to_dir 207 self.l3UnblockToDir = l3_unblock_to_dir 208 self.reqToL3 = req_to_l3 209 self.probeToL3 = probe_to_l3 210 self.respToL3 = resp_to_l3 211 212def define_options(parser): 213 parser.add_option("--num-subcaches", type="int", default=4) 214 parser.add_option("--l3-data-latency", type="int", default=20) 215 parser.add_option("--l3-tag-latency", type="int", default=15) 216 parser.add_option("--cpu-to-dir-latency", type="int", default=15) 217 parser.add_option("--no-resource-stalls", action="store_false", 218 default=True) 219 parser.add_option("--num-tbes", type="int", default=256) 220 parser.add_option("--l2-latency", type="int", default=50) # load to use 221 222def create_system(options, full_system, system, dma_devices, ruby_system): 223 if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base': 224 panic("This script requires the MOESI_AMD_Base protocol.") 225 226 cpu_sequencers = [] 227 228 # 229 # The ruby network creation expects the list of nodes in the system to 230 # be consistent with the NetDest list. Therefore the l1 controller 231 # nodes must be listed before the directory nodes and directory nodes 232 # before dma nodes, etc. 233 # 234 l1_cntrl_nodes = [] 235 l3_cntrl_nodes = [] 236 dir_cntrl_nodes = [] 237 238 control_count = 0 239 240 # 241 # Must create the individual controllers before the network to ensure 242 # the controller constructors are called before the network constructor 243 # 244 245 # This is the base crossbar that connects the L3s, Dirs, and cpu 246 # Cluster 247 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 248 for i in xrange(options.num_dirs): 249 250 dir_cntrl = DirCntrl(TCC_select_num_bits = 0) 251 dir_cntrl.create(options, ruby_system, system) 252 253 # Connect the Directory controller to the ruby network 254 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 255 dir_cntrl.requestFromCores.slave = ruby_system.network.master 256 257 dir_cntrl.responseFromCores = MessageBuffer() 258 dir_cntrl.responseFromCores.slave = ruby_system.network.master 259 260 dir_cntrl.unblockFromCores = MessageBuffer() 261 dir_cntrl.unblockFromCores.slave = ruby_system.network.master 262 263 dir_cntrl.probeToCore = MessageBuffer() 264 dir_cntrl.probeToCore.master = ruby_system.network.slave 265 266 dir_cntrl.responseToCore = MessageBuffer() 267 dir_cntrl.responseToCore.master = ruby_system.network.slave 268 269 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 270 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 271 dir_cntrl.responseFromMemory = MessageBuffer() 272 273 exec("system.dir_cntrl%d = dir_cntrl" % i) 274 dir_cntrl_nodes.append(dir_cntrl) 275 276 mainCluster.add(dir_cntrl) 277 278 # Technically this config can support an odd number of cpus, but the top 279 # level config files, such as the ruby_random_tester, will get confused if 280 # the number of cpus does not equal the number of sequencers. Thus make 281 # sure that an even number of cpus is specified. 282 assert((options.num_cpus % 2) == 0) 283 284 # For an odd number of CPUs, still create the right number of controllers 285 cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 286 for i in xrange((options.num_cpus + 1) / 2): 287 288 cp_cntrl = CPCntrl() 289 cp_cntrl.create(options, ruby_system, system) 290 291 exec("system.cp_cntrl%d = cp_cntrl" % i) 292 # 293 # Add controllers and sequencers to the appropriate lists 294 # 295 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 296 297 # Connect the CP controllers and the network 298 cp_cntrl.requestFromCore = MessageBuffer() 299 cp_cntrl.requestFromCore.master = ruby_system.network.slave 300 301 cp_cntrl.responseFromCore = MessageBuffer() 302 cp_cntrl.responseFromCore.master = ruby_system.network.slave 303 304 cp_cntrl.unblockFromCore = MessageBuffer() 305 cp_cntrl.unblockFromCore.master = ruby_system.network.slave 306 307 cp_cntrl.probeToCore = MessageBuffer() 308 cp_cntrl.probeToCore.slave = ruby_system.network.master 309 310 cp_cntrl.responseToCore = MessageBuffer() 311 cp_cntrl.responseToCore.slave = ruby_system.network.master 312 313 cp_cntrl.mandatoryQueue = MessageBuffer() 314 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 315 316 cpuCluster.add(cp_cntrl) 317 318 # Assuming no DMA devices 319 assert(len(dma_devices) == 0) 320 321 # Add cpu/gpu clusters to main cluster 322 mainCluster.add(cpuCluster) 323 324 ruby_system.network.number_of_virtual_networks = 10 325 326 return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 327