MOESI_AMD_Base.py revision 13731
112697Santhony.gutierrez@amd.com# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 212697Santhony.gutierrez@amd.com# All rights reserved. 311308Santhony.gutierrez@amd.com# 412697Santhony.gutierrez@amd.com# For use for simulation and test purposes only 511308Santhony.gutierrez@amd.com# 612697Santhony.gutierrez@amd.com# Redistribution and use in source and binary forms, with or without 712697Santhony.gutierrez@amd.com# modification, are permitted provided that the following conditions are met: 811308Santhony.gutierrez@amd.com# 912697Santhony.gutierrez@amd.com# 1. Redistributions of source code must retain the above copyright notice, 1012697Santhony.gutierrez@amd.com# this list of conditions and the following disclaimer. 1111308Santhony.gutierrez@amd.com# 1212697Santhony.gutierrez@amd.com# 2. Redistributions in binary form must reproduce the above copyright notice, 1312697Santhony.gutierrez@amd.com# this list of conditions and the following disclaimer in the documentation 1412697Santhony.gutierrez@amd.com# and/or other materials provided with the distribution. 1511308Santhony.gutierrez@amd.com# 1612697Santhony.gutierrez@amd.com# 3. Neither the name of the copyright holder nor the names of its 1712697Santhony.gutierrez@amd.com# contributors may be used to endorse or promote products derived from this 1812697Santhony.gutierrez@amd.com# software without specific prior written permission. 1911308Santhony.gutierrez@amd.com# 2012697Santhony.gutierrez@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2112697Santhony.gutierrez@amd.com# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2212697Santhony.gutierrez@amd.com# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2312697Santhony.gutierrez@amd.com# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2412697Santhony.gutierrez@amd.com# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2512697Santhony.gutierrez@amd.com# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2612697Santhony.gutierrez@amd.com# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2712697Santhony.gutierrez@amd.com# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2812697Santhony.gutierrez@amd.com# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2912697Santhony.gutierrez@amd.com# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3012697Santhony.gutierrez@amd.com# POSSIBILITY OF SUCH DAMAGE. 3111308Santhony.gutierrez@amd.com# 3212697Santhony.gutierrez@amd.com# Authors: Lisa Hsu 3311308Santhony.gutierrez@amd.com 3411308Santhony.gutierrez@amd.comimport math 3511308Santhony.gutierrez@amd.comimport m5 3611308Santhony.gutierrez@amd.comfrom m5.objects import * 3711308Santhony.gutierrez@amd.comfrom m5.defines import buildEnv 3813400Sodanrc@yahoo.com.brfrom m5.util import addToPath 3911308Santhony.gutierrez@amd.comfrom Ruby import create_topology 4011308Santhony.gutierrez@amd.comfrom Ruby import send_evicts 4111308Santhony.gutierrez@amd.com 4213400Sodanrc@yahoo.com.braddToPath('../') 4313400Sodanrc@yahoo.com.br 4411670Sandreas.hansson@arm.comfrom topologies.Cluster import Cluster 4511670Sandreas.hansson@arm.comfrom topologies.Crossbar import Crossbar 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.comclass CntrlBase: 4811308Santhony.gutierrez@amd.com _seqs = 0 4911308Santhony.gutierrez@amd.com @classmethod 5011308Santhony.gutierrez@amd.com def seqCount(cls): 5111308Santhony.gutierrez@amd.com # Use SeqCount not class since we need global count 5211308Santhony.gutierrez@amd.com CntrlBase._seqs += 1 5311308Santhony.gutierrez@amd.com return CntrlBase._seqs - 1 5411308Santhony.gutierrez@amd.com 5511308Santhony.gutierrez@amd.com _cntrls = 0 5611308Santhony.gutierrez@amd.com @classmethod 5711308Santhony.gutierrez@amd.com def cntrlCount(cls): 5811308Santhony.gutierrez@amd.com # Use CntlCount not class since we need global count 5911308Santhony.gutierrez@amd.com CntrlBase._cntrls += 1 6011308Santhony.gutierrez@amd.com return CntrlBase._cntrls - 1 6111308Santhony.gutierrez@amd.com 6211308Santhony.gutierrez@amd.com _version = 0 6311308Santhony.gutierrez@amd.com @classmethod 6411308Santhony.gutierrez@amd.com def versionCount(cls): 6511308Santhony.gutierrez@amd.com cls._version += 1 # Use count for this particular type 6611308Santhony.gutierrez@amd.com return cls._version - 1 6711308Santhony.gutierrez@amd.com 6811308Santhony.gutierrez@amd.comclass L1DCache(RubyCache): 6911308Santhony.gutierrez@amd.com resourceStalls = False 7011308Santhony.gutierrez@amd.com def create(self, options): 7111308Santhony.gutierrez@amd.com self.size = MemorySize(options.l1d_size) 7211308Santhony.gutierrez@amd.com self.assoc = options.l1d_assoc 7311308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 7411308Santhony.gutierrez@amd.com 7511308Santhony.gutierrez@amd.comclass L1ICache(RubyCache): 7611308Santhony.gutierrez@amd.com resourceStalls = False 7711308Santhony.gutierrez@amd.com def create(self, options): 7811308Santhony.gutierrez@amd.com self.size = MemorySize(options.l1i_size) 7911308Santhony.gutierrez@amd.com self.assoc = options.l1i_assoc 8011308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 8111308Santhony.gutierrez@amd.com 8211308Santhony.gutierrez@amd.comclass L2Cache(RubyCache): 8311308Santhony.gutierrez@amd.com resourceStalls = False 8411308Santhony.gutierrez@amd.com def create(self, options): 8511308Santhony.gutierrez@amd.com self.size = MemorySize(options.l2_size) 8611308Santhony.gutierrez@amd.com self.assoc = options.l2_assoc 8711308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 8811308Santhony.gutierrez@amd.com 8911308Santhony.gutierrez@amd.comclass CPCntrl(CorePair_Controller, CntrlBase): 9011308Santhony.gutierrez@amd.com 9111308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 9211308Santhony.gutierrez@amd.com self.version = self.versionCount() 9311308Santhony.gutierrez@amd.com 9411308Santhony.gutierrez@amd.com self.L1Icache = L1ICache() 9511308Santhony.gutierrez@amd.com self.L1Icache.create(options) 9611308Santhony.gutierrez@amd.com self.L1D0cache = L1DCache() 9711308Santhony.gutierrez@amd.com self.L1D0cache.create(options) 9811308Santhony.gutierrez@amd.com self.L1D1cache = L1DCache() 9911308Santhony.gutierrez@amd.com self.L1D1cache.create(options) 10011308Santhony.gutierrez@amd.com self.L2cache = L2Cache() 10111308Santhony.gutierrez@amd.com self.L2cache.create(options) 10211308Santhony.gutierrez@amd.com 10311308Santhony.gutierrez@amd.com self.sequencer = RubySequencer() 10411308Santhony.gutierrez@amd.com self.sequencer.icache_hit_latency = 2 10511308Santhony.gutierrez@amd.com self.sequencer.dcache_hit_latency = 2 10611308Santhony.gutierrez@amd.com self.sequencer.version = self.seqCount() 10711308Santhony.gutierrez@amd.com self.sequencer.icache = self.L1Icache 10811308Santhony.gutierrez@amd.com self.sequencer.dcache = self.L1D0cache 10911308Santhony.gutierrez@amd.com self.sequencer.ruby_system = ruby_system 11011308Santhony.gutierrez@amd.com self.sequencer.coreid = 0 11111308Santhony.gutierrez@amd.com self.sequencer.is_cpu_sequencer = True 11211308Santhony.gutierrez@amd.com 11311308Santhony.gutierrez@amd.com self.sequencer1 = RubySequencer() 11411308Santhony.gutierrez@amd.com self.sequencer1.version = self.seqCount() 11511308Santhony.gutierrez@amd.com self.sequencer1.icache = self.L1Icache 11611308Santhony.gutierrez@amd.com self.sequencer1.dcache = self.L1D1cache 11711308Santhony.gutierrez@amd.com self.sequencer1.icache_hit_latency = 2 11811308Santhony.gutierrez@amd.com self.sequencer1.dcache_hit_latency = 2 11911308Santhony.gutierrez@amd.com self.sequencer1.ruby_system = ruby_system 12011308Santhony.gutierrez@amd.com self.sequencer1.coreid = 1 12111308Santhony.gutierrez@amd.com self.sequencer1.is_cpu_sequencer = True 12211308Santhony.gutierrez@amd.com 12311308Santhony.gutierrez@amd.com self.issue_latency = options.cpu_to_dir_latency 12411308Santhony.gutierrez@amd.com self.send_evictions = send_evicts(options) 12511308Santhony.gutierrez@amd.com 12611308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 12711308Santhony.gutierrez@amd.com 12811308Santhony.gutierrez@amd.com if options.recycle_latency: 12911308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 13011308Santhony.gutierrez@amd.com 13111308Santhony.gutierrez@amd.comclass L3Cache(RubyCache): 13211308Santhony.gutierrez@amd.com assoc = 8 13311308Santhony.gutierrez@amd.com dataArrayBanks = 256 13411308Santhony.gutierrez@amd.com tagArrayBanks = 256 13511308Santhony.gutierrez@amd.com 13611308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 13711308Santhony.gutierrez@amd.com self.size = MemorySize(options.l3_size) 13811308Santhony.gutierrez@amd.com self.size.value /= options.num_dirs 13911308Santhony.gutierrez@amd.com self.dataArrayBanks /= options.num_dirs 14011308Santhony.gutierrez@amd.com self.tagArrayBanks /= options.num_dirs 14111308Santhony.gutierrez@amd.com self.dataArrayBanks /= options.num_dirs 14211308Santhony.gutierrez@amd.com self.tagArrayBanks /= options.num_dirs 14311308Santhony.gutierrez@amd.com self.dataAccessLatency = options.l3_data_latency 14411308Santhony.gutierrez@amd.com self.tagAccessLatency = options.l3_tag_latency 14511308Santhony.gutierrez@amd.com self.resourceStalls = options.no_resource_stalls 14611308Santhony.gutierrez@amd.com self.replacement_policy = PseudoLRUReplacementPolicy() 14711308Santhony.gutierrez@amd.com 14811308Santhony.gutierrez@amd.comclass L3Cntrl(L3Cache_Controller, CntrlBase): 14911308Santhony.gutierrez@amd.com def create(self, options, ruby_system, system): 15011308Santhony.gutierrez@amd.com self.version = self.versionCount() 15111308Santhony.gutierrez@amd.com self.L3cache = L3Cache() 15211308Santhony.gutierrez@amd.com self.L3cache.create(options, ruby_system, system) 15311308Santhony.gutierrez@amd.com 15411308Santhony.gutierrez@amd.com self.l3_response_latency = max(self.L3cache.dataAccessLatency, 15511308Santhony.gutierrez@amd.com self.L3cache.tagAccessLatency) 15611308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 15711308Santhony.gutierrez@amd.com 15811308Santhony.gutierrez@amd.com if options.recycle_latency: 15911308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 16011308Santhony.gutierrez@amd.com 16111308Santhony.gutierrez@amd.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 16211308Santhony.gutierrez@amd.com req_to_l3, probe_to_l3, resp_to_l3): 16311308Santhony.gutierrez@amd.com self.reqToDir = req_to_dir 16411308Santhony.gutierrez@amd.com self.respToDir = resp_to_dir 16511308Santhony.gutierrez@amd.com self.l3UnblockToDir = l3_unblock_to_dir 16611308Santhony.gutierrez@amd.com self.reqToL3 = req_to_l3 16711308Santhony.gutierrez@amd.com self.probeToL3 = probe_to_l3 16811308Santhony.gutierrez@amd.com self.respToL3 = resp_to_l3 16911308Santhony.gutierrez@amd.com 17011308Santhony.gutierrez@amd.comclass DirCntrl(Directory_Controller, CntrlBase): 17112065Snikos.nikoleris@arm.com def create(self, options, dir_ranges, ruby_system, system): 17211308Santhony.gutierrez@amd.com self.version = self.versionCount() 17311308Santhony.gutierrez@amd.com 17411308Santhony.gutierrez@amd.com self.response_latency = 30 17511308Santhony.gutierrez@amd.com 17612065Snikos.nikoleris@arm.com self.addr_ranges = dir_ranges 17712065Snikos.nikoleris@arm.com self.directory = RubyDirectoryMemory() 17811308Santhony.gutierrez@amd.com 17911308Santhony.gutierrez@amd.com self.L3CacheMemory = L3Cache() 18011308Santhony.gutierrez@amd.com self.L3CacheMemory.create(options, ruby_system, system) 18111308Santhony.gutierrez@amd.com 18211308Santhony.gutierrez@amd.com self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 18311308Santhony.gutierrez@amd.com self.L3CacheMemory.tagAccessLatency) 18411308Santhony.gutierrez@amd.com 18511308Santhony.gutierrez@amd.com self.number_of_TBEs = options.num_tbes 18611308Santhony.gutierrez@amd.com 18711308Santhony.gutierrez@amd.com self.ruby_system = ruby_system 18811308Santhony.gutierrez@amd.com 18911308Santhony.gutierrez@amd.com if options.recycle_latency: 19011308Santhony.gutierrez@amd.com self.recycle_latency = options.recycle_latency 19111308Santhony.gutierrez@amd.com 19211308Santhony.gutierrez@amd.com self.CPUonly = True 19311308Santhony.gutierrez@amd.com 19411308Santhony.gutierrez@amd.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 19511308Santhony.gutierrez@amd.com req_to_l3, probe_to_l3, resp_to_l3): 19611308Santhony.gutierrez@amd.com self.reqToDir = req_to_dir 19711308Santhony.gutierrez@amd.com self.respToDir = resp_to_dir 19811308Santhony.gutierrez@amd.com self.l3UnblockToDir = l3_unblock_to_dir 19911308Santhony.gutierrez@amd.com self.reqToL3 = req_to_l3 20011308Santhony.gutierrez@amd.com self.probeToL3 = probe_to_l3 20111308Santhony.gutierrez@amd.com self.respToL3 = resp_to_l3 20211308Santhony.gutierrez@amd.com 20311308Santhony.gutierrez@amd.comdef define_options(parser): 20411308Santhony.gutierrez@amd.com parser.add_option("--num-subcaches", type="int", default=4) 20511308Santhony.gutierrez@amd.com parser.add_option("--l3-data-latency", type="int", default=20) 20611308Santhony.gutierrez@amd.com parser.add_option("--l3-tag-latency", type="int", default=15) 20711308Santhony.gutierrez@amd.com parser.add_option("--cpu-to-dir-latency", type="int", default=15) 20811308Santhony.gutierrez@amd.com parser.add_option("--no-resource-stalls", action="store_false", 20911308Santhony.gutierrez@amd.com default=True) 21011308Santhony.gutierrez@amd.com parser.add_option("--num-tbes", type="int", default=256) 21111308Santhony.gutierrez@amd.com parser.add_option("--l2-latency", type="int", default=50) # load to use 21211308Santhony.gutierrez@amd.com 21312598Snikos.nikoleris@arm.comdef create_system(options, full_system, system, dma_devices, bootmem, 21412598Snikos.nikoleris@arm.com ruby_system): 21511308Santhony.gutierrez@amd.com if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base': 21611308Santhony.gutierrez@amd.com panic("This script requires the MOESI_AMD_Base protocol.") 21711308Santhony.gutierrez@amd.com 21811308Santhony.gutierrez@amd.com cpu_sequencers = [] 21911308Santhony.gutierrez@amd.com 22011308Santhony.gutierrez@amd.com # 22111308Santhony.gutierrez@amd.com # The ruby network creation expects the list of nodes in the system to 22211308Santhony.gutierrez@amd.com # be consistent with the NetDest list. Therefore the l1 controller 22311308Santhony.gutierrez@amd.com # nodes must be listed before the directory nodes and directory nodes 22411308Santhony.gutierrez@amd.com # before dma nodes, etc. 22511308Santhony.gutierrez@amd.com # 22611308Santhony.gutierrez@amd.com l1_cntrl_nodes = [] 22711308Santhony.gutierrez@amd.com l3_cntrl_nodes = [] 22811308Santhony.gutierrez@amd.com dir_cntrl_nodes = [] 22911308Santhony.gutierrez@amd.com 23011308Santhony.gutierrez@amd.com control_count = 0 23111308Santhony.gutierrez@amd.com 23211308Santhony.gutierrez@amd.com # 23311308Santhony.gutierrez@amd.com # Must create the individual controllers before the network to ensure 23411308Santhony.gutierrez@amd.com # the controller constructors are called before the network constructor 23511308Santhony.gutierrez@amd.com # 23611308Santhony.gutierrez@amd.com 23711308Santhony.gutierrez@amd.com # This is the base crossbar that connects the L3s, Dirs, and cpu 23811308Santhony.gutierrez@amd.com # Cluster 23911308Santhony.gutierrez@amd.com mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 24012065Snikos.nikoleris@arm.com 24112065Snikos.nikoleris@arm.com if options.numa_high_bit: 24212065Snikos.nikoleris@arm.com numa_bit = options.numa_high_bit 24312065Snikos.nikoleris@arm.com else: 24412065Snikos.nikoleris@arm.com # if the numa_bit is not specified, set the directory bits as the 24512065Snikos.nikoleris@arm.com # lowest bits above the block offset bits, and the numa_bit as the 24612065Snikos.nikoleris@arm.com # highest of those directory bits 24712065Snikos.nikoleris@arm.com dir_bits = int(math.log(options.num_dirs, 2)) 24812065Snikos.nikoleris@arm.com block_size_bits = int(math.log(options.cacheline_size, 2)) 24912065Snikos.nikoleris@arm.com numa_bit = block_size_bits + dir_bits - 1 25012065Snikos.nikoleris@arm.com 25113731Sandreas.sandberg@arm.com for i in range(options.num_dirs): 25212065Snikos.nikoleris@arm.com dir_ranges = [] 25312065Snikos.nikoleris@arm.com for r in system.mem_ranges: 25412065Snikos.nikoleris@arm.com addr_range = m5.objects.AddrRange(r.start, size = r.size(), 25512065Snikos.nikoleris@arm.com intlvHighBit = numa_bit, 25612065Snikos.nikoleris@arm.com intlvBits = dir_bits, 25712065Snikos.nikoleris@arm.com intlvMatch = i) 25812065Snikos.nikoleris@arm.com dir_ranges.append(addr_range) 25912065Snikos.nikoleris@arm.com 26011308Santhony.gutierrez@amd.com 26111308Santhony.gutierrez@amd.com dir_cntrl = DirCntrl(TCC_select_num_bits = 0) 26212065Snikos.nikoleris@arm.com dir_cntrl.create(options, dir_ranges, ruby_system, system) 26311308Santhony.gutierrez@amd.com 26411308Santhony.gutierrez@amd.com # Connect the Directory controller to the ruby network 26511308Santhony.gutierrez@amd.com dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 26611308Santhony.gutierrez@amd.com dir_cntrl.requestFromCores.slave = ruby_system.network.master 26711308Santhony.gutierrez@amd.com 26811308Santhony.gutierrez@amd.com dir_cntrl.responseFromCores = MessageBuffer() 26911308Santhony.gutierrez@amd.com dir_cntrl.responseFromCores.slave = ruby_system.network.master 27011308Santhony.gutierrez@amd.com 27111308Santhony.gutierrez@amd.com dir_cntrl.unblockFromCores = MessageBuffer() 27211308Santhony.gutierrez@amd.com dir_cntrl.unblockFromCores.slave = ruby_system.network.master 27311308Santhony.gutierrez@amd.com 27411308Santhony.gutierrez@amd.com dir_cntrl.probeToCore = MessageBuffer() 27511308Santhony.gutierrez@amd.com dir_cntrl.probeToCore.master = ruby_system.network.slave 27611308Santhony.gutierrez@amd.com 27711308Santhony.gutierrez@amd.com dir_cntrl.responseToCore = MessageBuffer() 27811308Santhony.gutierrez@amd.com dir_cntrl.responseToCore.master = ruby_system.network.slave 27911308Santhony.gutierrez@amd.com 28011308Santhony.gutierrez@amd.com dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 28111308Santhony.gutierrez@amd.com dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 28211308Santhony.gutierrez@amd.com dir_cntrl.responseFromMemory = MessageBuffer() 28311308Santhony.gutierrez@amd.com 28411308Santhony.gutierrez@amd.com exec("system.dir_cntrl%d = dir_cntrl" % i) 28511308Santhony.gutierrez@amd.com dir_cntrl_nodes.append(dir_cntrl) 28611308Santhony.gutierrez@amd.com 28711308Santhony.gutierrez@amd.com mainCluster.add(dir_cntrl) 28811308Santhony.gutierrez@amd.com 28911308Santhony.gutierrez@amd.com # Technically this config can support an odd number of cpus, but the top 29011308Santhony.gutierrez@amd.com # level config files, such as the ruby_random_tester, will get confused if 29111308Santhony.gutierrez@amd.com # the number of cpus does not equal the number of sequencers. Thus make 29211308Santhony.gutierrez@amd.com # sure that an even number of cpus is specified. 29311308Santhony.gutierrez@amd.com assert((options.num_cpus % 2) == 0) 29411308Santhony.gutierrez@amd.com 29511308Santhony.gutierrez@amd.com # For an odd number of CPUs, still create the right number of controllers 29611308Santhony.gutierrez@amd.com cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 29713731Sandreas.sandberg@arm.com for i in range((options.num_cpus + 1) // 2): 29811308Santhony.gutierrez@amd.com 29911308Santhony.gutierrez@amd.com cp_cntrl = CPCntrl() 30011308Santhony.gutierrez@amd.com cp_cntrl.create(options, ruby_system, system) 30111308Santhony.gutierrez@amd.com 30211308Santhony.gutierrez@amd.com exec("system.cp_cntrl%d = cp_cntrl" % i) 30311308Santhony.gutierrez@amd.com # 30411308Santhony.gutierrez@amd.com # Add controllers and sequencers to the appropriate lists 30511308Santhony.gutierrez@amd.com # 30611308Santhony.gutierrez@amd.com cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 30711308Santhony.gutierrez@amd.com 30811308Santhony.gutierrez@amd.com # Connect the CP controllers and the network 30911308Santhony.gutierrez@amd.com cp_cntrl.requestFromCore = MessageBuffer() 31011308Santhony.gutierrez@amd.com cp_cntrl.requestFromCore.master = ruby_system.network.slave 31111308Santhony.gutierrez@amd.com 31211308Santhony.gutierrez@amd.com cp_cntrl.responseFromCore = MessageBuffer() 31311308Santhony.gutierrez@amd.com cp_cntrl.responseFromCore.master = ruby_system.network.slave 31411308Santhony.gutierrez@amd.com 31511308Santhony.gutierrez@amd.com cp_cntrl.unblockFromCore = MessageBuffer() 31611308Santhony.gutierrez@amd.com cp_cntrl.unblockFromCore.master = ruby_system.network.slave 31711308Santhony.gutierrez@amd.com 31811308Santhony.gutierrez@amd.com cp_cntrl.probeToCore = MessageBuffer() 31911308Santhony.gutierrez@amd.com cp_cntrl.probeToCore.slave = ruby_system.network.master 32011308Santhony.gutierrez@amd.com 32111308Santhony.gutierrez@amd.com cp_cntrl.responseToCore = MessageBuffer() 32211308Santhony.gutierrez@amd.com cp_cntrl.responseToCore.slave = ruby_system.network.master 32311308Santhony.gutierrez@amd.com 32411308Santhony.gutierrez@amd.com cp_cntrl.mandatoryQueue = MessageBuffer() 32511308Santhony.gutierrez@amd.com cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 32611308Santhony.gutierrez@amd.com 32711308Santhony.gutierrez@amd.com cpuCluster.add(cp_cntrl) 32811308Santhony.gutierrez@amd.com 32911308Santhony.gutierrez@amd.com # Assuming no DMA devices 33011308Santhony.gutierrez@amd.com assert(len(dma_devices) == 0) 33111308Santhony.gutierrez@amd.com 33211308Santhony.gutierrez@amd.com # Add cpu/gpu clusters to main cluster 33311308Santhony.gutierrez@amd.com mainCluster.add(cpuCluster) 33411308Santhony.gutierrez@amd.com 33511308Santhony.gutierrez@amd.com ruby_system.network.number_of_virtual_networks = 10 33611308Santhony.gutierrez@amd.com 33711308Santhony.gutierrez@amd.com return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 338