MOESI_AMD_Base.py revision 12697 
1# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
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9# 1. Redistributions of source code must retain the above copyright notice,
10# this list of conditions and the following disclaimer.
11#
12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
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15#
16# 3. Neither the name of the copyright holder nor the names of its
17# contributors may be used to endorse or promote products derived from this
18# software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Lisa Hsu
33
34import math
35import m5
36from m5.objects import *
37from m5.defines import buildEnv
38from Ruby import create_topology
39from Ruby import send_evicts
40
41from topologies.Cluster import Cluster
42from topologies.Crossbar import Crossbar
43
44class CntrlBase:
45    _seqs = 0
46    @classmethod
47    def seqCount(cls):
48        # Use SeqCount not class since we need global count
49        CntrlBase._seqs += 1
50        return CntrlBase._seqs - 1
51
52    _cntrls = 0
53    @classmethod
54    def cntrlCount(cls):
55        # Use CntlCount not class since we need global count
56        CntrlBase._cntrls += 1
57        return CntrlBase._cntrls - 1
58
59    _version = 0
60    @classmethod
61    def versionCount(cls):
62        cls._version += 1 # Use count for this particular type
63        return cls._version - 1
64
65class L1DCache(RubyCache):
66    resourceStalls = False
67    def create(self, options):
68        self.size = MemorySize(options.l1d_size)
69        self.assoc = options.l1d_assoc
70        self.replacement_policy = PseudoLRUReplacementPolicy()
71
72class L1ICache(RubyCache):
73    resourceStalls = False
74    def create(self, options):
75        self.size = MemorySize(options.l1i_size)
76        self.assoc = options.l1i_assoc
77        self.replacement_policy = PseudoLRUReplacementPolicy()
78
79class L2Cache(RubyCache):
80    resourceStalls = False
81    def create(self, options):
82        self.size = MemorySize(options.l2_size)
83        self.assoc = options.l2_assoc
84        self.replacement_policy = PseudoLRUReplacementPolicy()
85
86class CPCntrl(CorePair_Controller, CntrlBase):
87
88    def create(self, options, ruby_system, system):
89        self.version = self.versionCount()
90
91        self.L1Icache = L1ICache()
92        self.L1Icache.create(options)
93        self.L1D0cache = L1DCache()
94        self.L1D0cache.create(options)
95        self.L1D1cache = L1DCache()
96        self.L1D1cache.create(options)
97        self.L2cache = L2Cache()
98        self.L2cache.create(options)
99
100        self.sequencer = RubySequencer()
101        self.sequencer.icache_hit_latency = 2
102        self.sequencer.dcache_hit_latency = 2
103        self.sequencer.version = self.seqCount()
104        self.sequencer.icache = self.L1Icache
105        self.sequencer.dcache = self.L1D0cache
106        self.sequencer.ruby_system = ruby_system
107        self.sequencer.coreid = 0
108        self.sequencer.is_cpu_sequencer = True
109
110        self.sequencer1 = RubySequencer()
111        self.sequencer1.version = self.seqCount()
112        self.sequencer1.icache = self.L1Icache
113        self.sequencer1.dcache = self.L1D1cache
114        self.sequencer1.icache_hit_latency = 2
115        self.sequencer1.dcache_hit_latency = 2
116        self.sequencer1.ruby_system = ruby_system
117        self.sequencer1.coreid = 1
118        self.sequencer1.is_cpu_sequencer = True
119
120        self.issue_latency = options.cpu_to_dir_latency
121        self.send_evictions = send_evicts(options)
122
123        self.ruby_system = ruby_system
124
125        if options.recycle_latency:
126            self.recycle_latency = options.recycle_latency
127
128class L3Cache(RubyCache):
129    assoc = 8
130    dataArrayBanks = 256
131    tagArrayBanks = 256
132
133    def create(self, options, ruby_system, system):
134        self.size = MemorySize(options.l3_size)
135        self.size.value /= options.num_dirs
136        self.dataArrayBanks /= options.num_dirs
137        self.tagArrayBanks /= options.num_dirs
138        self.dataArrayBanks /= options.num_dirs
139        self.tagArrayBanks /= options.num_dirs
140        self.dataAccessLatency = options.l3_data_latency
141        self.tagAccessLatency = options.l3_tag_latency
142        self.resourceStalls = options.no_resource_stalls
143        self.replacement_policy = PseudoLRUReplacementPolicy()
144
145class L3Cntrl(L3Cache_Controller, CntrlBase):
146    def create(self, options, ruby_system, system):
147        self.version = self.versionCount()
148        self.L3cache = L3Cache()
149        self.L3cache.create(options, ruby_system, system)
150
151        self.l3_response_latency = max(self.L3cache.dataAccessLatency,
152                                       self.L3cache.tagAccessLatency)
153        self.ruby_system = ruby_system
154
155        if options.recycle_latency:
156            self.recycle_latency = options.recycle_latency
157
158    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
159                           req_to_l3, probe_to_l3, resp_to_l3):
160        self.reqToDir = req_to_dir
161        self.respToDir = resp_to_dir
162        self.l3UnblockToDir = l3_unblock_to_dir
163        self.reqToL3 = req_to_l3
164        self.probeToL3 = probe_to_l3
165        self.respToL3 = resp_to_l3
166
167class DirCntrl(Directory_Controller, CntrlBase):
168    def create(self, options, dir_ranges, ruby_system, system):
169        self.version = self.versionCount()
170
171        self.response_latency = 30
172
173        self.addr_ranges = dir_ranges
174        self.directory = RubyDirectoryMemory()
175
176        self.L3CacheMemory = L3Cache()
177        self.L3CacheMemory.create(options, ruby_system, system)
178
179        self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency,
180                                  self.L3CacheMemory.tagAccessLatency)
181
182        self.number_of_TBEs = options.num_tbes
183
184        self.ruby_system = ruby_system
185
186        if options.recycle_latency:
187            self.recycle_latency = options.recycle_latency
188
189        self.CPUonly = True
190
191    def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir,
192                           req_to_l3, probe_to_l3, resp_to_l3):
193        self.reqToDir = req_to_dir
194        self.respToDir = resp_to_dir
195        self.l3UnblockToDir = l3_unblock_to_dir
196        self.reqToL3 = req_to_l3
197        self.probeToL3 = probe_to_l3
198        self.respToL3 = resp_to_l3
199
200def define_options(parser):
201    parser.add_option("--num-subcaches", type="int", default=4)
202    parser.add_option("--l3-data-latency", type="int", default=20)
203    parser.add_option("--l3-tag-latency", type="int", default=15)
204    parser.add_option("--cpu-to-dir-latency", type="int", default=15)
205    parser.add_option("--no-resource-stalls", action="store_false",
206                      default=True)
207    parser.add_option("--num-tbes", type="int", default=256)
208    parser.add_option("--l2-latency", type="int", default=50) # load to use
209
210def create_system(options, full_system, system, dma_devices, bootmem,
211                  ruby_system):
212    if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base':
213        panic("This script requires the MOESI_AMD_Base protocol.")
214
215    cpu_sequencers = []
216
217    #
218    # The ruby network creation expects the list of nodes in the system to
219    # be consistent with the NetDest list.  Therefore the l1 controller
220    # nodes must be listed before the directory nodes and directory nodes
221    # before dma nodes, etc.
222    #
223    l1_cntrl_nodes = []
224    l3_cntrl_nodes = []
225    dir_cntrl_nodes = []
226
227    control_count = 0
228
229    #
230    # Must create the individual controllers before the network to ensure
231    # the controller constructors are called before the network constructor
232    #
233
234    # This is the base crossbar that connects the L3s, Dirs, and cpu
235    # Cluster
236    mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
237
238    if options.numa_high_bit:
239        numa_bit = options.numa_high_bit
240    else:
241        # if the numa_bit is not specified, set the directory bits as the
242        # lowest bits above the block offset bits, and the numa_bit as the
243        # highest of those directory bits
244        dir_bits = int(math.log(options.num_dirs, 2))
245        block_size_bits = int(math.log(options.cacheline_size, 2))
246        numa_bit = block_size_bits + dir_bits - 1
247
248    for i in xrange(options.num_dirs):
249        dir_ranges = []
250        for r in system.mem_ranges:
251            addr_range = m5.objects.AddrRange(r.start, size = r.size(),
252                                              intlvHighBit = numa_bit,
253                                              intlvBits = dir_bits,
254                                              intlvMatch = i)
255            dir_ranges.append(addr_range)
256
257
258        dir_cntrl = DirCntrl(TCC_select_num_bits = 0)
259        dir_cntrl.create(options, dir_ranges, ruby_system, system)
260
261        # Connect the Directory controller to the ruby network
262        dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
263        dir_cntrl.requestFromCores.slave = ruby_system.network.master
264
265        dir_cntrl.responseFromCores = MessageBuffer()
266        dir_cntrl.responseFromCores.slave = ruby_system.network.master
267
268        dir_cntrl.unblockFromCores = MessageBuffer()
269        dir_cntrl.unblockFromCores.slave = ruby_system.network.master
270
271        dir_cntrl.probeToCore = MessageBuffer()
272        dir_cntrl.probeToCore.master = ruby_system.network.slave
273
274        dir_cntrl.responseToCore = MessageBuffer()
275        dir_cntrl.responseToCore.master = ruby_system.network.slave
276
277        dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
278        dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
279        dir_cntrl.responseFromMemory = MessageBuffer()
280
281        exec("system.dir_cntrl%d = dir_cntrl" % i)
282        dir_cntrl_nodes.append(dir_cntrl)
283
284        mainCluster.add(dir_cntrl)
285
286    # Technically this config can support an odd number of cpus, but the top
287    # level config files, such as the ruby_random_tester, will get confused if
288    # the number of cpus does not equal the number of sequencers.  Thus make
289    # sure that an even number of cpus is specified.
290    assert((options.num_cpus % 2) == 0)
291
292    # For an odd number of CPUs, still create the right number of controllers
293    cpuCluster = Cluster(extBW = 512, intBW = 512)  # 1 TB/s
294    for i in xrange((options.num_cpus + 1) / 2):
295
296        cp_cntrl = CPCntrl()
297        cp_cntrl.create(options, ruby_system, system)
298
299        exec("system.cp_cntrl%d = cp_cntrl" % i)
300        #
301        # Add controllers and sequencers to the appropriate lists
302        #
303        cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
304
305        # Connect the CP controllers and the network
306        cp_cntrl.requestFromCore = MessageBuffer()
307        cp_cntrl.requestFromCore.master = ruby_system.network.slave
308
309        cp_cntrl.responseFromCore = MessageBuffer()
310        cp_cntrl.responseFromCore.master = ruby_system.network.slave
311
312        cp_cntrl.unblockFromCore = MessageBuffer()
313        cp_cntrl.unblockFromCore.master = ruby_system.network.slave
314
315        cp_cntrl.probeToCore = MessageBuffer()
316        cp_cntrl.probeToCore.slave = ruby_system.network.master
317
318        cp_cntrl.responseToCore = MessageBuffer()
319        cp_cntrl.responseToCore.slave = ruby_system.network.master
320
321        cp_cntrl.mandatoryQueue = MessageBuffer()
322        cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
323
324        cpuCluster.add(cp_cntrl)
325
326    # Assuming no DMA devices
327    assert(len(dma_devices) == 0)
328
329    # Add cpu/gpu clusters to main cluster
330    mainCluster.add(cpuCluster)
331
332    ruby_system.network.number_of_virtual_networks = 10
333
334    return (cpu_sequencers, dir_cntrl_nodes, mainCluster)
335