MOESI_AMD_Base.py revision 11670
11758SN/A# 21762SN/A# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 31758SN/A# All rights reserved. 41758SN/A# 51758SN/A# For use for simulation and test purposes only 61758SN/A# 71758SN/A# Redistribution and use in source and binary forms, with or without 81758SN/A# modification, are permitted provided that the following conditions are met: 91758SN/A# 101758SN/A# 1. Redistributions of source code must retain the above copyright notice, 111758SN/A# this list of conditions and the following disclaimer. 121758SN/A# 131758SN/A# 2. Redistributions in binary form must reproduce the above copyright notice, 141758SN/A# this list of conditions and the following disclaimer in the documentation 151758SN/A# and/or other materials provided with the distribution. 161758SN/A# 171758SN/A# 3. Neither the name of the copyright holder nor the names of its contributors 181758SN/A# may be used to endorse or promote products derived from this software 191758SN/A# without specific prior written permission. 201758SN/A# 211758SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 221758SN/A# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 231758SN/A# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 241758SN/A# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 251758SN/A# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 261758SN/A# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 272665Ssaidi@eecs.umich.edu# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 282665Ssaidi@eecs.umich.edu# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 292665Ssaidi@eecs.umich.edu# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 302665Ssaidi@eecs.umich.edu# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 311758SN/A# POSSIBILITY OF SUCH DAMAGE. 322SN/A# 331147SN/A# Author: Lisa Hsu 341147SN/A# 352SN/A 361858SN/Aimport math 372107SN/Aimport m5 381858SN/Afrom m5.objects import * 395566Snate@binkert.orgfrom m5.defines import buildEnv 402107SN/Afrom Ruby import create_topology 411858SN/Afrom Ruby import send_evicts 421147SN/A 43924SN/Afrom topologies.Cluster import Cluster 441147SN/Afrom topologies.Crossbar import Crossbar 45924SN/A 46924SN/Aclass CntrlBase: 471147SN/A _seqs = 0 481147SN/A @classmethod 491147SN/A def seqCount(cls): 501147SN/A # Use SeqCount not class since we need global count 515568Snate@binkert.org CntrlBase._seqs += 1 525568Snate@binkert.org return CntrlBase._seqs - 1 531147SN/A 541147SN/A _cntrls = 0 55924SN/A @classmethod 561858SN/A def cntrlCount(cls): 571147SN/A # Use CntlCount not class since we need global count 581147SN/A CntrlBase._cntrls += 1 59924SN/A return CntrlBase._cntrls - 1 601147SN/A 611147SN/A _version = 0 62924SN/A @classmethod 631147SN/A def versionCount(cls): 641147SN/A cls._version += 1 # Use count for this particular type 651147SN/A return cls._version - 1 661147SN/A 671147SN/Aclass L1DCache(RubyCache): 681805SN/A resourceStalls = False 691805SN/A def create(self, options): 701858SN/A self.size = MemorySize(options.l1d_size) 711805SN/A self.assoc = options.l1d_assoc 721805SN/A self.replacement_policy = PseudoLRUReplacementPolicy() 731805SN/A 741805SN/Aclass L1ICache(RubyCache): 751805SN/A resourceStalls = False 765568Snate@binkert.org def create(self, options): 771805SN/A self.size = MemorySize(options.l1i_size) 78924SN/A self.assoc = options.l1i_assoc 791147SN/A self.replacement_policy = PseudoLRUReplacementPolicy() 801147SN/A 815568Snate@binkert.orgclass L2Cache(RubyCache): 821147SN/A resourceStalls = False 831147SN/A def create(self, options): 841147SN/A self.size = MemorySize(options.l2_size) 851147SN/A self.assoc = options.l2_assoc 861147SN/A self.replacement_policy = PseudoLRUReplacementPolicy() 871147SN/A 882SN/Aclass CPCntrl(CorePair_Controller, CntrlBase): 891147SN/A 901147SN/A def create(self, options, ruby_system, system): 915568Snate@binkert.org self.version = self.versionCount() 921147SN/A 931147SN/A self.L1Icache = L1ICache() 941147SN/A self.L1Icache.create(options) 951147SN/A self.L1D0cache = L1DCache() 961147SN/A self.L1D0cache.create(options) 972SN/A self.L1D1cache = L1DCache() 981147SN/A self.L1D1cache.create(options) 992SN/A self.L2cache = L2Cache() 1001147SN/A self.L2cache.create(options) 1011147SN/A 1021147SN/A self.sequencer = RubySequencer() 1032SN/A self.sequencer.icache_hit_latency = 2 1041147SN/A self.sequencer.dcache_hit_latency = 2 1051147SN/A self.sequencer.version = self.seqCount() 1061147SN/A self.sequencer.icache = self.L1Icache 1072SN/A self.sequencer.dcache = self.L1D0cache 1081147SN/A self.sequencer.ruby_system = ruby_system 1091147SN/A self.sequencer.coreid = 0 1101147SN/A self.sequencer.is_cpu_sequencer = True 1111147SN/A 1121147SN/A self.sequencer1 = RubySequencer() 1131147SN/A self.sequencer1.version = self.seqCount() 1145568Snate@binkert.org self.sequencer1.icache = self.L1Icache 1155568Snate@binkert.org self.sequencer1.dcache = self.L1D1cache 1162SN/A self.sequencer1.icache_hit_latency = 2 1171147SN/A self.sequencer1.dcache_hit_latency = 2 1181147SN/A self.sequencer1.ruby_system = ruby_system 1192SN/A self.sequencer1.coreid = 1 1205566Snate@binkert.org self.sequencer1.is_cpu_sequencer = True 1212SN/A 1221147SN/A self.issue_latency = options.cpu_to_dir_latency 123 self.send_evictions = send_evicts(options) 124 125 self.ruby_system = ruby_system 126 127 if options.recycle_latency: 128 self.recycle_latency = options.recycle_latency 129 130class L3Cache(RubyCache): 131 assoc = 8 132 dataArrayBanks = 256 133 tagArrayBanks = 256 134 135 def create(self, options, ruby_system, system): 136 self.size = MemorySize(options.l3_size) 137 self.size.value /= options.num_dirs 138 self.dataArrayBanks /= options.num_dirs 139 self.tagArrayBanks /= options.num_dirs 140 self.dataArrayBanks /= options.num_dirs 141 self.tagArrayBanks /= options.num_dirs 142 self.dataAccessLatency = options.l3_data_latency 143 self.tagAccessLatency = options.l3_tag_latency 144 self.resourceStalls = options.no_resource_stalls 145 self.replacement_policy = PseudoLRUReplacementPolicy() 146 147class L3Cntrl(L3Cache_Controller, CntrlBase): 148 def create(self, options, ruby_system, system): 149 self.version = self.versionCount() 150 self.L3cache = L3Cache() 151 self.L3cache.create(options, ruby_system, system) 152 153 self.l3_response_latency = max(self.L3cache.dataAccessLatency, 154 self.L3cache.tagAccessLatency) 155 self.ruby_system = ruby_system 156 157 if options.recycle_latency: 158 self.recycle_latency = options.recycle_latency 159 160 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 161 req_to_l3, probe_to_l3, resp_to_l3): 162 self.reqToDir = req_to_dir 163 self.respToDir = resp_to_dir 164 self.l3UnblockToDir = l3_unblock_to_dir 165 self.reqToL3 = req_to_l3 166 self.probeToL3 = probe_to_l3 167 self.respToL3 = resp_to_l3 168 169class DirMem(RubyDirectoryMemory, CntrlBase): 170 def create(self, options, ruby_system, system): 171 self.version = self.versionCount() 172 173 phys_mem_size = AddrRange(options.mem_size).size() 174 mem_module_size = phys_mem_size / options.num_dirs 175 dir_size = MemorySize('0B') 176 dir_size.value = mem_module_size 177 self.size = dir_size 178 179class DirCntrl(Directory_Controller, CntrlBase): 180 def create(self, options, ruby_system, system): 181 self.version = self.versionCount() 182 183 self.response_latency = 30 184 185 self.directory = DirMem() 186 self.directory.create(options, ruby_system, system) 187 188 self.L3CacheMemory = L3Cache() 189 self.L3CacheMemory.create(options, ruby_system, system) 190 191 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 192 self.L3CacheMemory.tagAccessLatency) 193 194 self.number_of_TBEs = options.num_tbes 195 196 self.ruby_system = ruby_system 197 198 if options.recycle_latency: 199 self.recycle_latency = options.recycle_latency 200 201 self.CPUonly = True 202 203 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 204 req_to_l3, probe_to_l3, resp_to_l3): 205 self.reqToDir = req_to_dir 206 self.respToDir = resp_to_dir 207 self.l3UnblockToDir = l3_unblock_to_dir 208 self.reqToL3 = req_to_l3 209 self.probeToL3 = probe_to_l3 210 self.respToL3 = resp_to_l3 211 212def define_options(parser): 213 parser.add_option("--num-subcaches", type="int", default=4) 214 parser.add_option("--l3-data-latency", type="int", default=20) 215 parser.add_option("--l3-tag-latency", type="int", default=15) 216 parser.add_option("--cpu-to-dir-latency", type="int", default=15) 217 parser.add_option("--no-resource-stalls", action="store_false", 218 default=True) 219 parser.add_option("--num-tbes", type="int", default=256) 220 parser.add_option("--l2-latency", type="int", default=50) # load to use 221 222def create_system(options, full_system, system, dma_devices, ruby_system): 223 if buildEnv['PROTOCOL'] != 'MOESI_AMD_Base': 224 panic("This script requires the MOESI_AMD_Base protocol.") 225 226 cpu_sequencers = [] 227 228 # 229 # The ruby network creation expects the list of nodes in the system to 230 # be consistent with the NetDest list. Therefore the l1 controller 231 # nodes must be listed before the directory nodes and directory nodes 232 # before dma nodes, etc. 233 # 234 l1_cntrl_nodes = [] 235 l3_cntrl_nodes = [] 236 dir_cntrl_nodes = [] 237 238 control_count = 0 239 240 # 241 # Must create the individual controllers before the network to ensure 242 # the controller constructors are called before the network constructor 243 # 244 245 # This is the base crossbar that connects the L3s, Dirs, and cpu 246 # Cluster 247 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 248 for i in xrange(options.num_dirs): 249 250 dir_cntrl = DirCntrl(TCC_select_num_bits = 0) 251 dir_cntrl.create(options, ruby_system, system) 252 253 # Connect the Directory controller to the ruby network 254 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 255 dir_cntrl.requestFromCores.slave = ruby_system.network.master 256 257 dir_cntrl.responseFromCores = MessageBuffer() 258 dir_cntrl.responseFromCores.slave = ruby_system.network.master 259 260 dir_cntrl.unblockFromCores = MessageBuffer() 261 dir_cntrl.unblockFromCores.slave = ruby_system.network.master 262 263 dir_cntrl.probeToCore = MessageBuffer() 264 dir_cntrl.probeToCore.master = ruby_system.network.slave 265 266 dir_cntrl.responseToCore = MessageBuffer() 267 dir_cntrl.responseToCore.master = ruby_system.network.slave 268 269 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 270 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 271 dir_cntrl.responseFromMemory = MessageBuffer() 272 273 exec("system.dir_cntrl%d = dir_cntrl" % i) 274 dir_cntrl_nodes.append(dir_cntrl) 275 276 mainCluster.add(dir_cntrl) 277 278 # Technically this config can support an odd number of cpus, but the top 279 # level config files, such as the ruby_random_tester, will get confused if 280 # the number of cpus does not equal the number of sequencers. Thus make 281 # sure that an even number of cpus is specified. 282 assert((options.num_cpus % 2) == 0) 283 284 # For an odd number of CPUs, still create the right number of controllers 285 cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 286 for i in xrange((options.num_cpus + 1) / 2): 287 288 cp_cntrl = CPCntrl() 289 cp_cntrl.create(options, ruby_system, system) 290 291 exec("system.cp_cntrl%d = cp_cntrl" % i) 292 # 293 # Add controllers and sequencers to the appropriate lists 294 # 295 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 296 297 # Connect the CP controllers and the network 298 cp_cntrl.requestFromCore = MessageBuffer() 299 cp_cntrl.requestFromCore.master = ruby_system.network.slave 300 301 cp_cntrl.responseFromCore = MessageBuffer() 302 cp_cntrl.responseFromCore.master = ruby_system.network.slave 303 304 cp_cntrl.unblockFromCore = MessageBuffer() 305 cp_cntrl.unblockFromCore.master = ruby_system.network.slave 306 307 cp_cntrl.probeToCore = MessageBuffer() 308 cp_cntrl.probeToCore.slave = ruby_system.network.master 309 310 cp_cntrl.responseToCore = MessageBuffer() 311 cp_cntrl.responseToCore.slave = ruby_system.network.master 312 313 cp_cntrl.mandatoryQueue = MessageBuffer() 314 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 315 316 cpuCluster.add(cp_cntrl) 317 318 # Assuming no DMA devices 319 assert(len(dma_devices) == 0) 320 321 # Add cpu/gpu clusters to main cluster 322 mainCluster.add(cpuCluster) 323 324 ruby_system.network.number_of_virtual_networks = 10 325 326 return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 327