MI_example.py revision 9154:198352d722e4
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35 36# 37# Note: the cache latency is only used by the sequencer on fast path hits 38# 39class Cache(RubyCache): 40 latency = 3 41 42def define_options(parser): 43 return 44 45def create_system(options, system, piobus, dma_ports, ruby_system): 46 47 if buildEnv['PROTOCOL'] != 'MI_example': 48 panic("This script requires the MI_example protocol to be built.") 49 50 cpu_sequencers = [] 51 52 # 53 # The ruby network creation expects the list of nodes in the system to be 54 # consistent with the NetDest list. Therefore the l1 controller nodes must be 55 # listed before the directory nodes and directory nodes before dma nodes, etc. 56 # 57 l1_cntrl_nodes = [] 58 dir_cntrl_nodes = [] 59 dma_cntrl_nodes = [] 60 61 # 62 # Must create the individual controllers before the network to ensure the 63 # controller constructors are called before the network constructor 64 # 65 block_size_bits = int(math.log(options.cacheline_size, 2)) 66 67 cntrl_count = 0 68 69 for i in xrange(options.num_cpus): 70 # 71 # First create the Ruby objects associated with this cpu 72 # Only one cache exists for this protocol, so by default use the L1D 73 # config parameters. 74 # 75 cache = Cache(size = options.l1d_size, 76 assoc = options.l1d_assoc, 77 start_index_bit = block_size_bits) 78 79 # 80 # Only one unified L1 cache exists. Can cache instructions and data. 81 # 82 l1_cntrl = L1Cache_Controller(version = i, 83 cntrl_id = cntrl_count, 84 cacheMemory = cache, 85 send_evictions = ( 86 options.cpu_type == "detailed"), 87 ruby_system = ruby_system) 88 89 cpu_seq = RubySequencer(version = i, 90 icache = cache, 91 dcache = cache, 92 ruby_system = ruby_system) 93 94 l1_cntrl.sequencer = cpu_seq 95 96 if piobus != None: 97 cpu_seq.pio_port = piobus.slave 98 99 exec("system.l1_cntrl%d = l1_cntrl" % i) 100 # 101 # Add controllers and sequencers to the appropriate lists 102 # 103 cpu_sequencers.append(cpu_seq) 104 l1_cntrl_nodes.append(l1_cntrl) 105 106 cntrl_count += 1 107 108 phys_mem_size = 0 109 for mem in system.memories.unproxy(system): 110 phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1 111 mem_module_size = phys_mem_size / options.num_dirs 112 113 for i in xrange(options.num_dirs): 114 # 115 # Create the Ruby objects associated with the directory controller 116 # 117 118 mem_cntrl = RubyMemoryControl(version = i, 119 ruby_system = ruby_system) 120 121 dir_size = MemorySize('0B') 122 dir_size.value = mem_module_size 123 124 dir_cntrl = Directory_Controller(version = i, 125 cntrl_id = cntrl_count, 126 directory = \ 127 RubyDirectoryMemory( \ 128 version = i, 129 size = dir_size, 130 use_map = options.use_map, 131 map_levels = \ 132 options.map_levels), 133 memBuffer = mem_cntrl, 134 ruby_system = ruby_system) 135 136 exec("system.dir_cntrl%d = dir_cntrl" % i) 137 dir_cntrl_nodes.append(dir_cntrl) 138 139 cntrl_count += 1 140 141 for i, dma_port in enumerate(dma_ports): 142 # 143 # Create the Ruby objects associated with the dma controller 144 # 145 dma_seq = DMASequencer(version = i, 146 ruby_system = ruby_system) 147 148 dma_cntrl = DMA_Controller(version = i, 149 cntrl_id = cntrl_count, 150 dma_sequencer = dma_seq, 151 ruby_system = ruby_system) 152 153 exec("system.dma_cntrl%d = dma_cntrl" % i) 154 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 155 dma_cntrl_nodes.append(dma_cntrl) 156 cntrl_count += 1 157 158 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 159 160 topology = create_topology(all_cntrls, options) 161 162 return (cpu_sequencers, dir_cntrl_nodes, topology) 163