MI_example.py revision 12065:e3e51756dfef 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
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14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology, create_directories
35from Ruby import send_evicts
36
37#
38# Declare caches used by the protocol
39#
40class L1Cache(RubyCache): pass
41
42def define_options(parser):
43    return
44
45def create_system(options, full_system, system, dma_ports, ruby_system):
46
47    if buildEnv['PROTOCOL'] != 'MI_example':
48        panic("This script requires the MI_example protocol to be built.")
49
50    cpu_sequencers = []
51
52    #
53    # The ruby network creation expects the list of nodes in the system to be
54    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
55    # listed before the directory nodes and directory nodes before dma nodes, etc.
56    #
57    l1_cntrl_nodes = []
58    dma_cntrl_nodes = []
59
60    #
61    # Must create the individual controllers before the network to ensure the
62    # controller constructors are called before the network constructor
63    #
64    block_size_bits = int(math.log(options.cacheline_size, 2))
65
66    for i in xrange(options.num_cpus):
67        #
68        # First create the Ruby objects associated with this cpu
69        # Only one cache exists for this protocol, so by default use the L1D
70        # config parameters.
71        #
72        cache = L1Cache(size = options.l1d_size,
73                        assoc = options.l1d_assoc,
74                        start_index_bit = block_size_bits)
75
76
77        # the ruby random tester reuses num_cpus to specify the
78        # number of cpu ports connected to the tester object, which
79        # is stored in system.cpu. because there is only ever one
80        # tester object, num_cpus is not necessarily equal to the
81        # size of system.cpu; therefore if len(system.cpu) == 1
82        # we use system.cpu[0] to set the clk_domain, thereby ensuring
83        # we don't index off the end of the cpu list.
84        if len(system.cpu) == 1:
85            clk_domain = system.cpu[0].clk_domain
86        else:
87            clk_domain = system.cpu[i].clk_domain
88
89        # Only one unified L1 cache exists. Can cache instructions and data.
90        l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache,
91                                      send_evictions=send_evicts(options),
92                                      transitions_per_cycle=options.ports,
93                                      clk_domain=clk_domain,
94                                      ruby_system=ruby_system)
95
96        cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
97                                clk_domain=clk_domain, ruby_system=ruby_system)
98
99        l1_cntrl.sequencer = cpu_seq
100        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
101
102        # Add controllers and sequencers to the appropriate lists
103        cpu_sequencers.append(cpu_seq)
104        l1_cntrl_nodes.append(l1_cntrl)
105
106        # Connect the L1 controllers and the network
107        l1_cntrl.mandatoryQueue = MessageBuffer()
108        l1_cntrl.requestFromCache = MessageBuffer(ordered = True)
109        l1_cntrl.requestFromCache.master = ruby_system.network.slave
110        l1_cntrl.responseFromCache = MessageBuffer(ordered = True)
111        l1_cntrl.responseFromCache.master = ruby_system.network.slave
112        l1_cntrl.forwardToCache = MessageBuffer(ordered = True)
113        l1_cntrl.forwardToCache.slave = ruby_system.network.master
114        l1_cntrl.responseToCache = MessageBuffer(ordered = True)
115        l1_cntrl.responseToCache.slave = ruby_system.network.master
116
117    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
118    assert(phys_mem_size % options.num_dirs == 0)
119    mem_module_size = phys_mem_size / options.num_dirs
120
121    # Run each of the ruby memory controllers at a ratio of the frequency of
122    # the ruby system.
123    # clk_divider value is a fix to pass regression.
124    ruby_system.memctrl_clk_domain = DerivedClockDomain(
125                                          clk_domain=ruby_system.clk_domain,
126                                          clk_divider=3)
127
128    dir_cntrl_nodes = create_directories(options, system.mem_ranges,
129                                         ruby_system)
130    for dir_cntrl in dir_cntrl_nodes:
131        # Connect the directory controllers and the network
132        dir_cntrl.requestToDir = MessageBuffer(ordered = True)
133        dir_cntrl.requestToDir.slave = ruby_system.network.master
134        dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
135        dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
136
137        dir_cntrl.responseFromDir = MessageBuffer()
138        dir_cntrl.responseFromDir.master = ruby_system.network.slave
139        dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
140        dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
141        dir_cntrl.forwardFromDir = MessageBuffer()
142        dir_cntrl.forwardFromDir.master = ruby_system.network.slave
143        dir_cntrl.responseFromMemory = MessageBuffer()
144
145
146    for i, dma_port in enumerate(dma_ports):
147        #
148        # Create the Ruby objects associated with the dma controller
149        #
150        dma_seq = DMASequencer(version = i,
151                               ruby_system = ruby_system)
152
153        dma_cntrl = DMA_Controller(version = i,
154                                   dma_sequencer = dma_seq,
155                                   transitions_per_cycle = options.ports,
156                                   ruby_system = ruby_system)
157
158        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
159        exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
160        dma_cntrl_nodes.append(dma_cntrl)
161
162        # Connect the directory controllers and the network
163        dma_cntrl.mandatoryQueue = MessageBuffer()
164        dma_cntrl.requestToDir = MessageBuffer()
165        dma_cntrl.requestToDir.master = ruby_system.network.slave
166        dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
167        dma_cntrl.responseFromDir.slave = ruby_system.network.master
168
169    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
170
171    # Create the io controller and the sequencer
172    if full_system:
173        io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
174        ruby_system._io_port = io_seq
175        io_controller = DMA_Controller(version = len(dma_ports),
176                                       dma_sequencer = io_seq,
177                                       ruby_system = ruby_system)
178        ruby_system.io_controller = io_controller
179
180        # Connect the dma controller to the network
181        io_controller.mandatoryQueue = MessageBuffer()
182        io_controller.requestToDir = MessageBuffer()
183        io_controller.requestToDir.master = ruby_system.network.slave
184        io_controller.responseFromDir = MessageBuffer(ordered = True)
185        io_controller.responseFromDir.slave = ruby_system.network.master
186
187        all_cntrls = all_cntrls + [io_controller]
188
189    ruby_system.network.number_of_virtual_networks = 5
190    topology = create_topology(all_cntrls, options)
191    return (cpu_sequencers, dir_cntrl_nodes, topology)
192